Laboratory 4 Design a Muti-bit Counter and Programming a FPGA

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Laboratory 4 Design a Muti-bit Counter and Programming a FPGA For your report: The problem written in English The flowchart or function table to solve the problem if it is necessary The design entry included (VHDL and Schematic) The RTL Viewer has to be included The simulation result for designed digital component The analysis for the simulation The pin assignment- the table for assigning the circuit inputs and outputs to specific pins on the FPGA The configuration for the FPGA Device (JTAG) The test table you designed to record and verify the designed circuit on hardware Picture taken for your test if it is necessary The conclusion Background A. Approach I: Design 3-bit counter T-type flip-flop is shown in Figure 1. A T flip-flop is obtained from a JK flip-flop by tying the J and K inputs together to form the T input. Figure 1 Figure 2 shows BDF design for three-bit counter by using three T-type flip-flops Figure 2 Figure 3 is the simulation result. Check the relation among clock, Q0, Q1, and Q2 (set clr as high, en is high). For your simulation, you should consider clr as high and low, en as high and low, and observe the outputs of Q0, Q1, and Q2.

Figure 3 Suppose a clock frequency is clock = 24kHz The frequency of the 2 0 output line (Q0) is 1/2 of the input clock line (12kHz) The frequency of the 2 1 output line (Q1) is 1/4 of the input clock line (6kHz) The frequency of the 2 2 output line (Q2) is 1/8 of the input clock line (3kHz) B. Approach II: Design 3-bit counter VHDL design for three-bit counter (Figure 4) with and. Figure 4 Step 1. Start the Quartus II software. Select File New Project Wizard. And create a new project name under the directory C:\temp\your initial \Lab. Assign the project name counter3, assign Cyclone II for the device family, and select the EP2C35F672C6 chip in the Family & device settings, which is the FPGA used on Altera s DE2 board. Figure 5

Step 2. Open a new VHDL Device Design file (File > New) by highlighting VHDL File. And click OK. Type the VHDL code Step 3. Save the VHDL file (Figure 5) as.vhd as part of our project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save Step 4. Select File Create/Update Create Symbol Files for Current File (.bsf symbol) to create a symbol file for the VHDL code entered. A Compilation Report window initially displays Report not available ; however, be patient. A display window should soon appear stating that the Create Symbol File was (or not) successful. Click OK and close the Compilation Report window. Step 5. Open a new Schematic file (File > New) by highlighting Block Diagram/Schematic File. And click OK. Find the symbol file (bsf file you just created for VHDL in Step 4) from Project folder to support your design in BDF view. Insert the symbol and input/output pins OUTPUT Figure 6 Step 6. Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as counter3. Place a check mark in the space labeled Add file to current project and press Save. Step 7. create a Vector Waveform File (vwf) to simulate a design(bdf) file. Set an end time 30 µs for simulation from Edit and then run simulation based on Figure 3. You may have to expand the size of the Simulation Waveforms to suit your need and choose View > Fit in Window to see the entire 30µs waveform. Figure 7 is the simulation result. Check the relation among clock,,, count_out[0], count_out[1], count_out[2]. Integrated the decoder with 3-bit counter Step 1. design a decode in vhdl (Figure 8) Figure 7

Figure 8 Step 2. Save the VHDL file as dec7seg.vhd as part of our project under your subfolder. Place a check mark in the space labeled Add file to current project and press Save Step 3. Select File Create/Update Create Symbol Files for Current File (dec7seg.bsf symbol) to create a symbol file for the VHDL code entered. Step 4. Open a new Schematic file (File > New) by highlighting Block Diagram/Schematic File. And click OK. Find the symbol file (bsf file you created for VHDL) from Project folder to support your design in BDF view. Insert the symbol and input/output pins dec7seg dec[2..0] 1 display[0..6] OUTPUT display[0..6] Figure 9 Step 5. Before compiling this bdf file, we need to name this bdf file and save it as part of our project under your subfolder. Choose File > Save As and enter File name as counter3. Place a check mark in the space labeled Add file to current project and press Save. Step 6. Compile this integrated design (Figure 9) Step 7. You can make a pin configuration, compile your design, and download your design to FPGA board to test your digital system. Step 8. Use the pushbutton KEY0 as the Clock input, switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays HEX0 to display the hexadecimal count as your circuit operates.

Your Turn to Design Project: Consider the circuit in Figure 10. It is a 4-bit synchronous counter which uses four T-type flip-flops. The counter increments its count on each positive edge of the clock if the Enable signal is asserted. The counter is to 0 by using the Reset signal. Figure 10. A 4-bit counter 4-bit counter 1. Write a VHDL file or create a BDF file that defines a 4-bit counter by using the structure depicted in bdf (Figure 2) or vhdl(figure 5), and compile the circuit. What is the frequency relation between the clock and four outputs from four T-type flip-flops, respectively? 2. Create a waveform vector and simulate your circuit to verify its correctness of the design of 4-bit counter. 3. Is this counter counting up or counting down? 4. Augment your VHDL file or BDF file to use the pushbutton KEY0 as the Clock input, switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays HEX0 to display the hexadecimal count as your circuit operates. 5. Make the necessary pin assignments and compile the circuit. 6. Programming FPGA and test your implementation. You may use the following library in your VHDL design entry: LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; your code 12-bit counter design 7. Write a VHDL file or create a BDF file that defines a 12-bit counter by reusing the component of 4-bit counter, and compile the circuit. What is the frequency relation between the clock and all 12 outputs of Q namely Q 0, Q 1, Q 2, Q 3, Q 4, Q 5, Q 6, Q 7, Q 8, Q \9, Q 10, Q 11? 8. Create a waveform vector and simulate your circuit to verify its correctness of the design of 12-bit counter. 9. Augment your VHDL file to use the pushbutton KEY0 as the Clock input, switches SW1 and SW0 as Enable and Reset inputs, and 7-segment displays HEX2, HEX1, HEX0 (or LCD) to display the hexadecimal count as your circuit operates. 10. Make the necessary pin assignments and compile the circuit. 11. Programming FPGA and test your implementation.

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