ECE2029: Introduction to Digital Circuit Design Lab 4 Building a Sequential Logic Circuit A Four Digit 7-Segment Display Driver Objective: In this lab you will implement a driver circuit for the 4-digit 7-segment display on the Basys 3 boards. The individual segments (a-g) of the 4 digits share a common cathode which means that the segment values are actually sent to all 4 digits at once. It is only through activating the anodes AN0 AN3 individually that you can control what is displayed on each digit. To display a different digit on each of the 4 different displays will require you to implement a sequential circuit which will rapidly cycle through inputs of a 4 to 1 MUX and the anodes AN0-AN3 to activate one digit at a time yet the refresh rate will be fast enough that the user will not notice any flicker. You will again implement this lab completely in Verilog. However, you will need to use some new sequential Verilog constructs. Pre-lab Assignment: This pre-lab assignment is to be completed before your lab session and must be signed-off by the TA during your lab session. Pre-labs help you to become oriented to the problem before you enter lab, help complete your design in advance and prevent wasting time in lab. 1) READ the whole lab assignment! 2) READ Section 8.1 of the Basys 3 Reference Manual. 3) This lab requires a 4-to-1 (by 4-bit) multiplexer. Write out the truth table for this multiplexer. Using the information from Lab 3 and class notes write a Verilog module using a conditional assignment statement to implement a 4 to 1 (by 4 bit) multiplexer. Your module should have four 4-bit inputs called D0, D1, D2 and D3 plus the 2-bit selector input S. It should also have a single 4-bit output called Out. 4) This lab also requires a 2 to 4 decoder but because we are implementing the active low anode signals AN0 AN3 the decoder outputs will need to be inverted relative to a generic decoder, e.g. EN=1 and A 1 A 0 = 00 then Y = 1110. Write out the full truth table for this anode decoder with Enable. Now write a Verilog module using conditional statements with 3 single bit inputs En, A0, A1 and 4-bit output Y. Lab Assignment: The first task in this lab is to modify the single digit hex to 7-segment decoder from Lab 3 to implement the decimal point and the minus sign. Later we'll also need to separate the anode control from the segment settings because we will want a separate, sequential anode driver circuit (Figure 1).
decpt 0 decpt 1 decpt 2 decpt 3 sgn 0 sgn 1 sgn 2 sgn 3 4:1 Mux (1 bit) 4:1 Mux (1 bit) sgn decpt W X Y Z HEX DP 100 MHz Combinational Design: 1. Create a new project in Vivado and add your hex2seg.v module from Lab 3 to it. Edit the module declaration to add two new single bit inputs called sgn and decpt, and a new single bit output called DP. (Be careful, do not use sign or signed as they are treated as reserved words by Xilinx). REMEMBER TO COMPLETE COMMENT BLOCK WITH NAME AND MODULE DESCRIPTION FOR EACH VERILOG MODULE IN YOUR PROJECT!!! 2. Now modify the body of the module to implement the following logic. Whenever the sgn input is 1 the output segments segs should display only a minus sign (segment g only is active) regardless of what was applied on D or decpt. If decpt = 1 then you should display whatever is on D plus the decimal point DP. Remember that DP like the other segments is active low. You must apply logic 0 to light it. For now, leave anodes = 1110. Save this new and improved version of hex2seg.v. 3. Add a constraint file to your project with SW3-SW0 connected to D and decpt and sgn connected to BTNL and BTNR. Outputs segs and DP should be connected to the 7-segment display cathodes CA thru CG and DP and anodes connected to AN0 to AN3. Remember segment a is segs[6] and segment g is segs[0]. 4. Now generate the bit file, download your design and test by setting the value to be displayed on SW3-SW0. Buttons BTNL and BTNR should appropriately light the decimal point and minus sign. Save your project. Show the TA for sign-off.
6. In order to make the hex2seg decoder more general, we need to remove the output anodes (which hard codes the values for AN0-AN3) from hex2seg.v. Modify your module to remove this output and its assignment statement. Save the module. 7. Add a new Verilog module to your project called mux4to1.v and set it as Top Module. Implement the 4-to-1 (by 4 bit) multiplexer that you designed for pre-lab. Your module should have four 4-bit inputs called D0, D1, D2 and D3 plus the 2-bit selector input S. It should also have a single 4-bit output called Out. You may want to refer back to the class notes on Verilog and Lab 3 for examples of conditional statements. 8. Add a Verilog test bench for your MUX to your project under Sources for Simulation and set it as Top Module. Within the test bench assign D0 D3 to fixed values like 0001, 0010, 0100 and 1000. Assert all possible combinations the 2-bit selector input S. Run the Behavioral Simulation of your mux. Save your project. Be sure to include a screen capture of your mux test bench results in your report. 9. Add a new Verilog module to your project called decodeanode.v and set it as Top Module. Implement the active low 2-to-4 decoder that your designed for pre-lab. Your module should have 1 single bit inputs En, a two-bit input A, and a 4-bit output Y. 10. Add a Verilog test bench for your anode decoder to your project under Sources for Simulation and set it as Top Module. Assert all possible input combinations and run the Behavioral Simulation of your decoder. Save your project. Be sure to include a screen capture of your decoder test bench results in your report. Sequential Design: As we've discussed in class, a sequential circuit deps on a clock signal to sychronize updating the state of sequential elements like flip flops. The Basys 3 board, itself being a large sequential circuit, has a clock but its the clock speed (100 MHz) is too high for our design. We will need to divide the system clock down to generate a clock better suited for the 7-segment diplay driver. 11. Download the module clkdiv10k.v from the class website and add it to your project. This module divides the input clock frequency by 10,000 (i.e. If the input clock is 1000MHZ the output of the clock divider is a 10KHz clock signal). 12. Conceptually, we want to quickly cycle through the 4 digits activating each one's segments and anode in turn. You have a decoder that given the binary code of the digits 0-3 will generate the proper anode signals. What we need now is a circuit that will generate a repeating sequence of digit codes 00, 01, 10, 11, 00, 01, 10, 11,... which can be applied as the selector input to the digits multiplexer and as the input to the anode decoder. A class of circuit that generates a repeating binary sequence of values on its output is called a "Binary Counter". We need a 2-bit binary counter to generate the sequence of digit codes, 00 11. Add a new Verilog module to your project called bin_cnt2.v with 2 single bit inputs clk and Reset and a 2-bit output called Q. Copy the code below into the module and save. 13. Add a Verilog test fixture to your project and associate it with bin_cnt2.v. Simulate 12 clock periods by alternately setting clk = 0 and clk = 1 for 1000 ns. Reset
should equal 1 for at least 4 rising clock edges then be set to 0 for 8 clock periods. Save your project. Run the simulation of your 2-bit counter. When does your counter reset? As soon as Reset is applied or with the next rising edge? Be sure to include a screen capture of your counter test bench results and anwer the Reset question in your report. module bin_cnt2( input clk, input Reset, output [1:0] Q ); reg [1:0] cnt; // This module implements a 2-bit binary counter with a // synchronous reset module always @ (posedge clk) if (Reset == 1) cnt = 2'b00; else if (cnt == 2'b00) cnt = 2'b01; else if (cnt == 2'b01) cnt = 2'b10; else if (cnt == 2'b10) cnt = 2'b11; else if (cnt == 2'b11) cnt = 2'b00; assign Q = cnt; 14. You are now ready to test the anode driver part of the circuit. To do this you will use a single input digit and display its value on the 4 displays sequentially. However, you will need a slow clock to actually see the displays sequence. Add a new Verilog module under Design to your project called anodedriver.v. It should have two single bit inputs CLK and Reset and 7-bit output segs, single bit output DP and 4-bit output anodes. Set it as Top Module and complete the following instantiations to implement the anode driver test circuit.
wire clk_10k, clk_1hz; wire [1:0] Q; // Divide the 100MHz system clock to 10KHz clkdiv10k U1(CLK,clk_10K); // Divide the 10KHz clock to 1Hz clkdiv10k U2(clk_10K,clk_1Hz); // Generate the 7-seg for hex A (i.e. 4'b1010) // without sign or decimal hex2seg U3(4'b1010,0,0,segs,DP); // --- Actual anode driving part --- // 2-bit binary counter driving the 2-to-4 anode decoder bin_cnt2 U4(clk_1Hz,Reset,Q); // For now set En = 1, decodeanode U5(1,Q,anodes) 15. Remove (but don't delete) the old constraint file for hex2seg and add a constrain file for anodedriver that connects CLK to the 100 MHz system clock (W5), Reset to BTNR and anodes to AN3-AN0 and segs and DP to CA thru CG and DP. When you press and release Reset the your board should display the digit "A" sequentially on each of the 4 seven-segment displays from right to left. In the Basys 3 Manual it says that AN3 controls the left-most digit and AN0 the right-most. However, on my board AN0 controlled the left-most digit and AN3 the right-most. If you find the anodes are reversed on your board you can "correct" it by associating anodes[3] with AN0, anodes[2] with AN1, etc., in your constraints file. Generate a bit file and demonstrate your anode driver to the TA for sign-off. 16. Save you project. Add a new Verilog module under Design called fourdigitdisplay.v and make it the Top Module. This module will implement Figure 1. The module will need four 4-bit data inputs, W, X, Y, and Z, and 8 single bit inputs decpt3 - decpt0 and sgn3 - sgn0 and a single bit clock input, CLK. Alternatively, you could make the decimal points and signs each 4-bit buses. The module should have 7-bit output segs, single bit output DP and 4-bit output anodes. Using anodedriver.v as a guide implement the instatiations necessary to implement the input multiplexers for the data inputs as well as the sign and decimal point inputs. Save your project again! W X Y Four segs Z Digit DP Display decpts anodes sgns CLK Figure 2: Block diagram of four digit 7-segment display circuit.
// Implement other "wire" declarations that you need wire clk_10khz;... // Instantiate a clkdiv10k module to implement the clock // divider from the 100MHz system clock input on CLK to a // 10KHz clock... // Implement input multiplexing necessary to generate inputs // to hex2seg, namely D, decpt, sgn from module inputs // W,X,Y,Z and all the sign and decimal points (You will need // a 4 to 1, by 1-bit MUX for the signs and another for the // decimal points). BE CAREFUL about the order of inputs in // mapping W,X,Y and Z D3 to D0. The 2-bit selector input for // all these MUXes is the output Q from bin_cnt2. // The module's outputs segs and DP should be the outputs of // hex2seg just as they were in anodedriver... // --- Actual anode driving part --- // 2-bit binary counter driving the 2-to-4 anode decoder // Assign Reset = 0 bin_cnt2 U4(clk_10KHz,0,Q); // Set En = 1 anodedecode U5(1,Q,anodes) 17. Ideally, we would like to add a constraint file directly to our fourdigitdisplay but because our board does not have enough buttons to implement all 8 sign and decimal points input we need to add a simple wrapper module around fourdigitdisplay that will allow us to hardcode some of the inputs to 0. Add a new Verilog source to you project called displaytester.v and set it as the Top Module. Your module should have two 4-bit inputs X and Z and four single bit inputs sgnw, sgny, dpx and dpz plus 7 bit output segs, single bit output DP and 4 bit output anodes. Instantiate your fourdigitdisplay module within displaytester setting inputs W and Y plus the signs for digits 0 and 2 as well as the decimal points for digits 1 and 3 all to 0. 18. Remove (but don't delete) the old constraint file. Add a.xdc file for displaytester that connects 4-bit inputs X and Z to SW7-SW4 and SW3-SW0 respectively. The decimal points for those digits, dpx and dpz, should be connected to BTNL and BTNR respectively. Sign inputs for digits 3 and 1 (i.e. sgnw and sgny) should be connected to BTNU and BTND respectively. The output segs, DP and anodes should be connected as in the anodedriver.xdc file. Save your project.
19. Generate a bit file and down load your 4 digit display driver test circuit. The switches should control the values displayed on digits 2 and 0 and decimal points for those digits should be lit anytime BTNL and BTNR are pressed. When BTNU or BTND is pressed, a minus sign should appear on digit 3 or digit 1 respectively. Show your circuit to the TA for sign-off.
ECE2029 Lab 4 Sign-Off Sheet Make sure lab instructor/ta initials and dates each part. Attach this sheet and the Report Grading Rubric to your team's lab report! Both partners MUST be present at sign-off! Your Name: ECE BOX #: Lab Partner: Date Performed: Demonstrated correctly: Pre-lab Complete (1) (2) (10 pts) Hex to 7-seg Decoder with sign and decimal (15 pts) Anode Driver circuit (20 pts) Full 4 digit Hex Display with signs and decimals (20 pts) TA Questions: (1) (2) (5 pts ) Report (one per team) (30 pts) (including Verilog source code, test benches, constraint files& ISim screen shots)
Lab 4 Four Digit 7-Segment Display Driver Review Item Comments Points (max) 1) Prelabs from each student complete (5) and thoughtful 2) Introduction effectively presents the (5) objectives and purpose of the lab. Methodology gives enough details to allow for replication of procedure. 3) Discussion opens with an effective (5) statement on the goals of the lab, backs up statement with reference to appropriate findings, provides sufficient and logical explanation for the statement, addresses other issues pertinent to lab. 4) Results opens with effective statement of (5) overall findings, presents visuals clearly and accurately, presents findings clearly and with sufficient support. You MUST include screen shots of the test bench results for each part of the lab. Conclusion convincingly describes what has been learned in the lab. 5) Other: (10) References are included. Tables and figures are formatted. All Verilog code is properly commented. Grammar and spelling are correct Report is written clearly and to the point. Overall, the team... has successfully demonstrated what the lab was designed to teach demonstrates clear and thoughtful scientific inquiry has accurately measured and analyzed data for lab findings Total: (30)