CS/EE 260 - Homework 7 Solutions 4/2/2001 1. (20 points) A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. esign a circuit for a 4 bit twisted ring counter that uses four flip flops. raw a state transition diagram, a state table and a schematic for your circuit. esign an alternate implementation using just three flip flops and draw a state transition diagram, state table and a schematic for your circuit. If your designs are extended to implement an n bit twisted ring counter, how many flip flops are required using each of the two approaches. In what situations would you prefer the first method? In what situations would you prefer the second? present next state state output 0000 1000 0000 1000 1100 1000 1100 1110 1100 1110 1111 1110 1111 0111 1111 0111 0011 0111 0011 0001 0011 0001 0000 0001 0000/0000 1000/1000 1100/1100 1110/1110 0001/0001 0011/0011 0111/0111 1111/1111 outputs Reset Clk - 1 -
present next state state output 000 001 0000 001 010 1000 010 011 1100 011 100 1110 100 101 1111 101 110 110 111 0111 0011 111 000 0001 000/0000 111/0001 001/1000 110/0011 010/1100 101/0111 011/1110 100/1111 outputs Reset Clk If the designs are extended to n bits, the first will need n flip flops, while the second will need 1+log2n (assuming n is a power of 2). So for example, if n=64, this would be 64 vs. 7. On the other hand, the second will need more gates to generate the output logic, which could more than compensate for the savings in the number of flip flops. The first is preferable if speed is critical, but the second might be better for large values of n if it is important to minimize the number of flip flops.. - 2 -
2. (30 points) Write a VHL specification for a loadable BC up-down counter with 4 digits. Your design should have three control signals load, cnt and up. When load is high, the circuit should load the value on the data inputs. Otherwise, when cnt is high, the circuit should increment by 1 if up is high and decrement by 1 if up is low. Your design should also have a synchronous reset that sets the counter to zero when asserted. Simulate your design first using a functional simulation with a 10 ns clock period. In your simulation, load the following values into the counter 8, 98, 998, 9998 and after each load, increment the counter 5 times and decrement it 5 times. Verify that your counter works correctly and turn in the result from this simulation, along with your VHL source code. Now, switch to a unit delay mode simulation. oes your design still work correctly? If not, explain why you think it is not working. Also, if it does not work, try doubling the clock period and checking the results again. If it still does not work, continue doubling the clock period until you find a clock period for which your design will work in the unit delay mode. Turn in samples of your simulation output for each of these runs, showing either that the circuit is working correctly, or that it is not. What do these results tell you about the operation speed of your circuit? library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- bcd digit implements one decimal digit of BC up/down counter entity bcd_digit is port ( clk, reset: in ST_LOGIC; cnt, up, load: in ST_LOGIC; cbout: out ST_LOGIC; d: in ST_LOGIC_VECTOR (3 downto 0); q: out ST_LOGIC_VECTOR (3 downto 0) ); end bcd_digit; architecture bcd_digit_arch of bcd_digit is signal reg: ST_LOGIC_VECTOR (3 downto 0); begin process begin wait until clk = '1'; if reset = '1' then reg <= x"0"; elsif load = '1' then reg <= d; elsif cnt = '1' and up = '1' then if reg = x"9" then reg <= x"0"; else reg <= reg + x"1"; end if; elsif cnt = '1' and up = '0' then if reg = x"0" then reg <= x"9"; else - 3 -
reg <= reg - x"1"; end if; end if; end process; q <= reg; cbout <= '1' when (cnt = '1' and up = '1' and reg = x"9") or (cnt = '1' and up = '0' and reg = x"0") else '0'; end bcd_digit_arch; library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; -- BC up-down counter. Resets to zero, counts when cnt high, -- counts up when up is also high, otherwise down entity bcdcntv is port ( clk, reset: in ST_LOGIC; cnt, up, load: in ST_LOGIC; d: in ST_LOGIC_VECTOR (15 downto 0); q: out ST_LOGIC_VECTOR (15 downto 0) ); end bcdcntv; architecture bcdcntv_arch of bcdcntv is component bcd_digit port ( clk, reset: in ST_LOGIC; cnt, up, load: in ST_LOGIC; cbout: out ST_LOGIC; d: in ST_LOGIC_VECTOR (3 downto 0); q: out ST_LOGIC_VECTOR (3 downto 0) ); end component; signal cb: ST_LOGIC_VECTOR(3 downto 0); begin d0: bcd_digit port map(clk,reset, cnt, up,load,cb(0),d( 3 downto 0),q( 3 downto 0)); d1: bcd_digit port map(clk,reset,cb(0),up,load,cb(1),d( 7 downto 4),q( 7 downto 4)); d2: bcd_digit port map(clk,reset,cb(1),up,load,cb(2),d(11 downto 8),q(11 downto 8)); d3: bcd_digit port map(clk,reset,cb(2),up,load,cb(3),d(15 downto 12),q(15 downto 12)); end bcdcntv_arch; The functional simulation results appear on the next page, and show the circuit working correctly for all the tested input conditions. - 4 -
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The simulation results below are from a unit delay simulation with a simulation precision of 1 ns and a 10 ns clock period. Although this was run for the same input values as the functional simulation, the results are obviously incorrect. Presumably, the gate delays are too high to allow the values to propagate through the combinational logic within the 10 ns available in each clock period. The results below are for a 20 ns clock period, and we can see that it seems to work somewhat better, but the load operation is still not working correctly. Apparently, it takes more than the 10 ns available for the data input values to propagate through the circuit s combinational logic to the flip flops. The results below are for a 40 ns clock period and here the load operation does work correctly, as do the counting operations. So, it appears that 20 ns is enough time for input values to propagate through to the flip flops. Overall, the results show that the counter works correctly, if the inputs are stable 20 ns before the clock goes high and the clock period is 40 ns or more. Clock periods close to 20 ns could work as well, but the inputs will have to be stable more than 10 ns before the clock edge in this case. - 6 -