A User s Experience with SystemVerilog and Doulos Ltd Ringwood, U.K. BH24 1AW jonathan.bromley@doulos.com michael.smith@doulos.com
2 Objectives Practical use of SystemVerilog Synopsys tools (VCS, Design Compiler) Aim for no-compromise SystemVerilog methodology New data types wherever appropriate Use variables everywhere - no nets! Interfaces for better abstraction of interconnect Transaction-driven test fixture, assertion checking Awareness of the landscape Work around tool limitations - it s very early days yet! Note upcoming SystemVerilog 3.1a changes/enhancements
3 Outline Overview of design and test fixture Using SystemVerilog in the design peripheral bus slave outputs Input data registers data control CORDIC rotator Design under test (DUT) Challenges in bus modelling master Test stimulus generator stimulus Reference model of rotator expected results results from DUT Results checker Using SystemVerilog in verification Challenges in transaction-based verification
4 Design and Test Fixture peripheral bus slave outputs Input data registers data control CORDIC rotator Legend: Legend: Synthesisable SystemVerilog SystemVerilog test fixture Design under test (DUT) C software master Test stimulus generator stimulus Reference model of rotator expected results results from DUT Results checker
Practical Problems That Make It Interesting 5 Design needs 16 clock cycles to perform a calculation start/ready handshake flags appear in bus-visible registers Test fixture must mimic software behaviour Set up inputs Hit start Poll until ready Read outputs clock start inputs ready outputs calculation takes 16 clock cycles
6 Bus is a simple synchronous bus Intended for small numbers of slow peripherals Only one master Only two kinds of bus cycle: Every transfer takes PCLK 2 clock cycles PSEL Read Write Part of AMBA specification (ARM Ltd) PADDR PWRITE PWDATA PENABLE Tailored for on-chip applications PRDATA read cycle write cycle
7 Verilog-2001 At Last! Life is better signed values, signed arithmetic localparam ANSI-style port declarations multi-dimensional arrays generate named parameter association We have avoided recommending Verilog-2001 in training patchy tool support but support is now complete in many tools Irritations can t define localparam within generate block multi-dimensional array ports???
8 Synthesisable SystemVerilog Data types to match the problem packed struct, union for different registers on common bus Structural driver on variable full power of variable data type system available throughout a design Note: can t mix structural and procedural drivers on fields of a packed object typedef struct packed { logic [15:10] Opcode; logic [9:0] Operand; } T_Instr; typedef struct packed { logic [15:1] Junk; logic Ready; } T_StatusWord; module T_Instr Instr; T_StatusWord Stat; logic [15:0] Databus; assign Databus = Adr[0]? Instr: Stat;
9 Synthesisable SystemVerilog Inquiry function $bits()for parameterisation via types Makes VHDL users very happy! Where to put this typedef? SV3.1a will offer packages module localparam Width = $bits (T_Instr T_Instr Instr; logic [Width-1:0] Databus; assign Instr = Databus; typedef struct packed { logic [15:10] Opcode; logic [9:0] Operand; } T_Instr;
10 Interfaces for Design Interface port is like a handle to a module instance module Top; Rst_Itf R1; Device D1(R1.RTL Rst_Itf R2; Device D2(R2.RTL R1 Rst_Itf; logic Reset; modport RTL (input Reset R2 Rst_Itf; logic Reset; modport RTL (input Reset D1 module Device ( Rst_Itf.RTL Wires always @(Wires.Reset) R1.Reset D2 module Device ( Rst_Itf.RTL Wires always @(Wires.Reset) R2.Reset
11 Interfaces for Design Interface port is like a handle to a module instance module Top; Cross-module Rst_Itf R1; Cross-module references references -- synthesis Device D1(R1.RTL synthesis issues? issues? Rst_Itf R2; Device D2(R2.RTL R1 Rst_Itf; logic Reset; modport RTL (input Reset R2 Rst_Itf; logic Reset; modport RTL (input Reset D1 module Device ( Rst_Itf.RTL Wires always @(Wires.Reset) D2 module Device ( Rst_Itf.RTL Wires always @( Wires.Reset )
12 Interfaces for Design module Top; Rst_Itf R1; Device D1(R1.RTL Rst_Itf R2; Device D2(R2.RTL Cross-module Cross-module references references -- synthesis synthesis issues? issues? modport modport controls controls visibility visibility and and direction direction -- not not yet yet respected respected in in VCS7.1 VCS7.1 R1 Rst_Itf; logic Reset; modport RTL (input Reset R2 Rst_Itf; logic Reset; modport RTL (input Reset D1 module Device ( Rst_Itf.RTL Wires always @(Wires.Reset) D2 module Device ( Rst_Itf.RTL Wires always @(Wires.Reset)
13 Interfaces in the Test Fixture Opportunity for transaction-level modelling via import task module Top; Rst_Itf R; jb: jb: provide provide V95/SV3.1 V95/SV3.1 parallel parallel Rst_Itf; examples examples TestCase T(R.Beh logic Reset; Device D(R.RTL task Pulse(input time T endmodule module endtask Device (Rst_Itf.RTL Wires always @(posedge Wires.Reset) modport Beh ( import task Pulse; module TestCase (Rst_Itf.Beh RstGen initial begin modport RTL (input Reset RstGen.Pulse(20 end
14 Interfaces in the Test Fixture Opportunity for transaction-level modelling via import task module Top; Rst_Itf R; jb: jb: provide provide V95/SV3.1 V95/SV3.1 parallel parallel Rst_Itf; examples examples TestCase T(R.Beh logic Reset; Device D(R.RTL task Pulse(input time T endmodule module endtask Device (Rst_Itf.RTL Wires always @(posedge Wires.Reset) modport Beh ( import task Pulse; module TestCase (Rst_Itf.Beh RstGen initial begin modport RTL (input Reset RstGen.Pulse(20 Just Just like like traditional traditional BFM BFM end -- but but don t don t need need to to know know its its instance instance name name in in the the hierarchy hierarchy
15 Assertions Natural way to describe bus activity, transactions Permanently active checker property WriteDataStable; @(posedge PCLK) ((PENABLE && PWRITE) -> $stable(pwdata) endproperty PCLK PSEL PADDR PWRITE Coverage - did it happen? automatic, inflexible in SV3.1 3.1a adds coverpoint PWDATA PENABLE PRDATA read cycle write cycle
16 Sample Project Revisited peripheral bus slave outputs Input data registers data control CORDIC rotator Legend: Legend: Synthesisable SystemVerilog SystemVerilog test fixture Design under test (DUT) C software master Test stimulus generator stimulus Reference model of rotator expected results results from DUT Results checker
17 Easier C Interface peripheral bus slave master outputs Test stimulus generator stimulus Input data registers data control CORDIC rotator Design under test (DUT) Reference model of rotator expected results results from DUT Results checker extern "C" void vlog_cordic_model ( input int reducenotrotate, input int anglein, input int xin, input int yin, output int angleout, output int xout, output int yout This This is is VCS VCS 7.1 s 7.1 s DirectC DirectC - - SystemVerilog3.1 SystemVerilog3.1 has has similar similar DPI DPI // Evaluate expected result vlog_cordic_model( reduce, angle, x, y, exp_angle, exp_x, exp_y No No PLI PLI linkage linkage tables! tables!
18 Easier C Interface peripheral bus slave master outputs Test stimulus generator stimulus Input data registers C helper helper functions functions data control CORDIC rotator Design under test (DUT) Reference model of rotator expected results results from DUT void vlog_cordic_model ( scalar reducenotrotate, int anglein, int xin, Plain Plain C code code -- int yin, no no need need for for PLI PLI calls calls to to int* angleout, get get argument argument values! values! int* xout, int* yout ) { Results checker double a, x, y, xr, yr, s, c; // Get trig values from Verilog info x = verilog_to_trig(xin y = verilog_to_trig(yin #define scalar_0 0 #define scalar_1 1 #define scalar_z 2 #define scalar_x 3 if (reducenotrotate == scalar_1 ) { // Determine rotation to reduce y to 0 a = -atan2(y, x
19 Interfaces and Modports ; logic PCLK, PSEL, modport RTL_slave ( input PCLK, input PSEL, modport TF_master ( import task read, import task write task read ( input [15:0] adrs, output [15:0] data ) endtask end peripheral bus my_apb( slave master outputs Test stimulus generator stimulus Instances in test fixture Input Instances data data in test fixture registers CORDIC control rotator CORDIC DUT(my_apb.RTL_slave Design under test (DUT) Tester t(my_apb.tf_master Reference model of rotator expected results results from DUT Results checker module Tester(.TF_master Bus initial begin : TestSequence logic [15:0] status; Bus.read(16 hffe3, status end
20 Interfaces, Modports and How How to to distribute distribute this this functionality? functionality? master PRDATA Slave select address bits Readback multiplexer PCLK, PADDR, PWRITE, PWDATA, PENABLE modport modport should should model model the the slave s slave s hardware hardware PSEL PRDATA#1 PSEL#1 slave #1 This This functionality functionality can can easily easily go go in in each each slave slave PSEL decoder PRDATA#N PSEL#N slave #N All All these these modports modports are are different different
21 Interfaces, Modports and Slave select address bits How How to to distribute distribute this this functionality? functionality? master SystemVerilog 3.1a 3.1a has has generatable modports PRDATA PSEL Readback multiplexer PCLK, PADDR, PWRITE, PWDATA, PENABLE PRDATA#1 PSEL#1 slave #1 This This functionality functionality can can easily easily go go in in each each slave slave PSEL decoder PRDATA#N PSEL#N slave #N All All these these modports modports are are different different
22 Conclusions SystemVerilog 3.1 is useful now incremental improvements such as.* typedef, struct, union, packed $bits() simple s Synthesis? Synthesis? Constrained-random stimulus is important not investigated in this example We look forward to the full functionality of s Synthesis? Synthesis? DirectC is good, DPI will give same benefits AND standardisation Assertions are powerful and convenient but we need SV3.1a cover, coverpoint to match capabilities of specialised testbench automation tools