FPGA: FIELD PROGRAMMABLE GATE ARRAY Verilog: a hardware description language Reference: []
FIELD PROGRAMMABLE GATE ARRAY FPGA is a hardware logic device that is programmable Logic functions may be programmed FPGAs can practically implement any logical function Programmable even after the product is deployed eg, FPGA controlling a home security system may be upgraded with new logic functions while the device is deployed in a customer s residence 2
Programmable Logic Blocks They implement the desired logic functions Programmable switches and wires They interconnect logic blocks to realize circuits requiring several logic blocks Programmable IO Blocks They connect wires from the switches to the IO pins on the chip Pins They are needed to get data into and out of the FPGA 3
IO BLOCK PIN LOGIC BLOCK INTERCONNECTION SWITCHES IO BLOCK IO BLOCK IO BLOCK 4
INPUTS OUTPUTS Combinational Circuit Memory Circuit General structure of a logic block It may be any combination of combinational and sequential (memory) circuits It could be all combinational, all memory, or a combination of combinational and memory circuits It will implement a desired logic function 5
EXAMPLE : LOGIC BLOCK A DESIRED FUNCTION MAY BE IMPLEMENTED BY A LOOKUP TABLE (LUT) Storage Cells and are used to lookup the value of the desired function, and output that value on wire and cause the MUX to select one of the four inputs and send that to the output S 4x MUX S The desired function is programmed into the storage cells Example: say you want the FPGA to implement the function The column of the truth table would be written into the storage cells of a logic block within the FPGA The inputs x and y may come from an internal or external source (ie, outside of the FPGA on pins 32 and 45, for example), in which case, the appropriate IO Block will be programmed to receives these pins, and the appropriate interconnection switches would be programmed to route the inputs to the logic block Also, the output of the logic block F would be routed by other interconnection switches and IO block to another pin for output of the function to the external world 6
A more complex logic block 7
SECTION OF PROGRAMMED FPGA EXAMPLE: 8
PROGRAMMING PROCEDURE A user (ie, you) describes the desired function of the digital device using a hardware description language, such as Verilog, in an Integrated development Environment (IDE), such as Quartus A IDE s compiler is used to translate the description to a logic circuit that implements the desired function The compiler generates a netlist, which specifies the Values of the storage cells and other logic within the Logic Blocks Configuration of the switches which interconnect the Logic Blocks Connection of the wires to the IO pins through the IO Blocks A netlist is a set of instructions intended for a processor on the FPGA The netlist specifies how to program the FPGA chip to implement a desired function 9
PROGRAMMING PROCEDURE The netlist is downloaded to the FPGA and stored in a Programmable Read Only Memory (PROM) (eg FLASH), which resides within the FPGA On an FPGA reset, the processor on the FPGA reads the values of the PROM (ie, the netlist) and: Configures the Logic Block storage cells, Configures the interconnection switches, and Configures the IO Blocks; Thus, programming the FPGA for the desired circuit
HARDWARE PROGRAMMING LANGUAGES There are two main languages used today: VHDL VHSIC (very-high-speed integrated circuits) HarDware Programming Language Verilog We will use Verilog in this course
Example Development Board With an FPGA: Altera s DE2 Board 7-Segment Display FPGA Chip LEDs Slider switches Pushbutton switches 2
Description of Verilog: Outline Basics History, general description, lexical elements, data types, number representation, operators Modules Description Levels Structural Functional assign statements Behavioural always block Type of Variable in Procedural Descriptions Kinds of assignments Blocking and non-blocking 3
Verilog is a Hardware description language Developed in mid-98 Transferred to IEEE (Standard 364) Ratified in 995 (Verilog-95) Then revised in 2 (Verilog-2) Verilog syntax is similar to that of the C language However, the Verilog semantics (meaning) are very different than that of the C language It is best to think of Verilog as a language for specifying the hardware components, their interconnection, and structure of a circuit, rather than sequential algorithm Verilog is very complex We will learn only what we need to develop the TOC 4
Simple Verilog Circuit (Like Hello World) module helloworld ( //IO Ports input SW, SW2; output LED; ) //signal declaration wire w, w2, w3, w4, w5; //body assign w = SW, w2 = SW2; assign LED = w5; assign w3 = w & w2; assign w4 = w w2; assign w5 = w3 ^ w4; endmodule SW SW2 FPGA w w2 w & w2 w w2 Note: SW, SW2, and LED are the names that have been assigned to the respective pins on the FPGA chip w3 w4 w3 ^ w4 w5 LED 5
Identifier Standard way of naming objects in your Verilog programs (letters, digits, underscore, etc) Verilog is case sensitive Keywords Predefined identifiers (module, wire, assign, etc) Comments // this is a comment on one line only /* this is a multiline comment, */ 6
Four values : logic zero : logic z: high impedance state x: unknown state, typically used in simulations 7
AKA Net Group Represents physical connections between hardware components Outputs of continuous assignment statements (ie, outputs of assign statements) wire, and tri are the most common wire w; //-bit wire named w wire [7:] w; //8-bit wire (bus) named w tri w; //-bit wire; can have three states (,, z) tri [7:] w; //8-bit tri-state bus named w 8
Variable Group Represent abstract storage The inferred circuit may or may not contain physical storage components Outputs of procedural assignment statements reg and integer are the most common reg should not be confused with a physical register reg w; //-bit reg variable named w reg [7:] w; //8-bit reg variable named w integer w; //32-bit integer 9
Standard notation: [sign] [size] [base][value] Base: b or B: Binary h or H: Hexadecimal d or D: Decimal Size: number of bits (even if base is not Binary) 2
Number Representation Examples Number Stored Value Comment 5 b 5 b_ _ ignored 5 ha 9 h_aa _ ignored 5 b extended 5 bz zzzzz Z extended -5 b 2 s complement of (ie, -) 2
VERILOG MODULES Verilog allows you to describe hardware in terms of modules: A module can be one of two types: Top-level module Sub-modules (sub-circuit, aka module) A circuit will have one top-level module and zero or more sub-modules Sub-circuit (aka module) Any logic circuit can be split into sub-circuits (modules) The sub-circuits are described by Verilog code in modules Each module will have a set of inputs and a set of outputs The outputs of Module i can be connected to the inputs of Module j, etc Sub-circuits (modules) may be reused one or many times in a larger circuit The circuit that contains the collection of sub-modules is the top-level module 22
Top-level module Only the top-level module creates a circuit The other modules describe how to make the sub-circuits, but they don t actually make a circuit, until they are instantiated They can also instantiate other modules Code in the top-level module will instantiate and create the subcircuits and connect their outputs to inputs of other modules The inputs and outputs of the top-level module are connected to pins of the FPGA chip Outputs of other modules are connected to inputs of other modules 23
EXAMPLE OF VERILOG MODULES FPGA Output peripheral device O Logic Type Logic Type SB LED Bank Logic Type 3 Logic Type 2 4 LB F SB Switch Bank Input peripheral device O2 SB module main(input SB, output LB) LT mylt (SB, O); //makes an LT LT mylt2 (SB, O2); //makes an LT LT2 mylt2 (O, O2, F); //makes an LT2 LT3 mylt3 (F, LB); //makes an LT3 endmodule //end of main; module LT(Input, Output) //code of LT endmodule //end of LT module LT2(Input, Input2, Output) //code of LT2 endmodule //end of LT2 module LT3(Input, Output) //code of LT3 endmodule //end of LT3 Sub-circuit (Generic) Descriptions: Templates or Modules Top-level Module: Makes circuit Circuit to be described by Verilog and placed into FPGA 24
Physical Logic Circuit The main (top level) circuit is split into a number of sub-circuits The outputs of one sub-circuit are connected to inputs of other sub-circuits There are three types of sub-circuits The Logic Type sub-circuit is re-used twice in the main circuit The main circuit gets input data from the input peripheral device and sends its outputs to the output peripheral device through pins of the FPGA chip Verilog Description of the Logic Circuit The sub-circuits are described by Verilog sub-modules (aka just modules) There are three sub-modules because there are three physical sub-circuit types The sub-modules by themselves do not actually make a sub-circuit The top-level module makes the sub-circuits make instantiating the submodules The top-level module instantiates two Logic Type modules and one each of Logic Type 2 and 3 sub-modules 25
EXAMPLE 4-BIT REGISTER MODULE SUB-CIRCUIT DESCRIBED BY A SUB-MODULE D Clock 4 4 4-BIT REGISTER Q module reg4 (D, Clock, Q); input [3:] D; input Clock; output reg [3:] Q; always @ (posedge Clock) Q <= D; endmodule Sub-circuit modules are described generically, as if they were self-contained, independent, and not part of a specific circuit The inputs and outputs are described with generic labels Describing a circuit generically allows it to be re-used in different circuits This module could be the LT of the previous slide 26
Verilog allows you to describe hardware at different levels of abstraction: Structural Level (lowest level) Describe the desired circuit in terms of gates Functional Level (medium level) Describe the circuit in terms of Boolean functions, and assigning functions to variables Behavioral Level (highest level) Describe the circuit by describing the behavior of the hardware to implement a desired function 27
VERILOG DESCRIPTION OF FULL ADDER STRUCTURAL DESCRIPTION S (Sum) can be expressed in terms of XOR gates (z = Cin): S = ~x&~y&z ~x&y&~z x&~y&~z x&y&z = x ^ y ^ Cin Carry out Cout by AND, OR, and XOR gates: Cout = x&y x&z y&z = x&y (x^y) &z Syntax Note: In Verilog The bit-wise NOT operation is denoted as ~ The bit-wise AND operation is denoted as & The bit-wise OR operation is denoted as The bit-wise XOR operation is denoted as ^ 28
VERILOG DESCRIPTION OF FULL ADDER STRUCTURAL DESCRIPTION Block Diagram Description x y s Full Adder Cin Cout Boolean Equation Description s = x^y^cin Cout = xy + (x^y)cin Verilog Structural Description of Full Adder module fulladder(x, y, Cin, s, Cout); input x, y, Cin; output s, Cout; wire w, w2, w3; xor(w, x, y); xor(s, w, Cin); //Sum, s and(w2, x, y); and(w3, w, Cin); or(cout, w2, w3); //Carry out, Cout endmodule Note that generic names are used for the inputs and outputs of the sub-module The xor, and, and or are logic gates supplied by the Verilog compiler: xor(out, in, in2) and(out, in, in2) or(out, in, in2) 29
POSSIBLE IMPLEMENTATION NOTE: THIS CIRCUIT MAY BE FURTHER OPTIMIZED (IE, SMALLER NUMBER OF LOGIC BLOCKS C out S X X Y W W C in S W 2 W 3 C out Y C in W C in W 3 X Y W 2 3
Structural description is used when we want to (or can) describe a circuit exactly with the specified gates The compiler will implement the circuit with lookup tables which implement the specified gates in our description When we don t care about which gates are used, we can use a functional description, and allow the compiler to optimize the design in any way it chooses A functional description is a higher level of abstraction than the structural description 3
ASSIGN STATEMENT IS USED IN FUNCTIONAL DESCRIPTION The Verilog assign keyword is used to assign a function to a wire The assign keyword means that the right hand side of the equal sign is evaluated all the time, just like in a combinational circuit The output depends on the present combination (value) of the inputs The assign statement is concurrent, meaning that if you have multiple assign statements, they will be executed in parallel The order of assign statements is irrelevant; any order produces the same result assign S = ~x&~y&z ~x&y&~z x&~y&~z x&y&z; assign Cout = x&y x&cin y&cin; 32
VERILOG DESCRIPTION OF FULL ADDER FUNCTIONAL DESCRIPTION x y Cin Full Adder s Cout Block Diagram Description of Full Adder module fulladder(x, y, Cin, s, Cout); input x, y, Cin; output s, Cout; assign s = ~x&~y&z ~x&y&~z x&~y&~z x&y&z; assign Cout = x&y x&cin y&cin; endmodule Verilog Description of Full Adder Note: we don t need to minimize the equation, since we will rely on the compiler to apply any optimization 33
34 POSSIBLE IMPLEMENTATION NOTE: FURTHER OPTIMIZATION POSSIBLE, DEPENDING ON COMPILER X Y C out C in S X Y C out C in X Y S C in
If we don t know the structural elements (ie, logic gates) that comprise the circuit; Or if we don t know the Boolean equation of the circuit that describes the circuit; Or if we prefer not to describe that amount of detail: We can describe the circuit by describing its intended behavior The behavioral description is a higher level of abstraction than the functional description 35
PROCEDURAL STATEMENTS In Verilog, behavior is described using procedural statements, also called sequential statements Unlike structural and functional statements, whose order in the code is irrelevant, sequential statements are executed in the order in which they appear in the code Procedural statements must be contained within an always block 36
General form always @ (sensitivity_list) [begin] [procedural assignment statements] [if-else statements] [case statements] [others ] [end] If any signal specified in the sensitivity list changes or becomes true, then the statements in the always block are executed in the order in which they appear in the code 37
Full adder: always @ (x, y, Cin) [begin] S = x^y^cin; //Procedural Assignment Statement Cout = x&y (x^y) &Cin; [end] Using * means that all input signals in the always block are included in the sensitivity list: always @ (*) [begin] [end] 38
The use of * in the sensitivity list means that all signals, which are written as inputs between [begin] and [end] are monitored for any changes, and if any one of them change, the always block is executed: always @ (*) begin S <= x^y^cin; //Procedural Assignment Statement Cout <= x&y (x^y) &Cin; end In this example, the x, y, Cin signals are monitored for any changes 39
TYPE OF VARIABLE IN PROCEDURAL DESCRIPTIONS Any signal on the left hand side (LHS) that is assigned a value within an always block must be of type reg (or integer) reg means registered or remembered This is because the always block is only executed (valid) during a short period of time when a signal in the sensitivity list changes (or becomes true), and the value of the LHS must be remembered at other times when signals in the sensitivity list do not change, because at those times the circuit is not executed (ie, not valid) However, signals on the right hand side (RHS) can be of type wire or reg 4
EXAMPLE: REG AND WIRE VARIABLE DECLARATION module fulladder(x, y, Cin, S, Cout); input wire x, y, Cin; output reg S, Cout; always @ (x, y, Cin) [begin] S = x^y^cin; Cout = x&y (x^y) &Cin; [end] endmodule Even though the fulladder is a combinational circuit (ie, not a memory circuit), it sill may be described behaviourally Also, the variables S and Cout must be of type reg This does not mean that the physical realization of the variables S and Cout will be flip flops 4
BEHAVIORAL DESCRIPTION OF FLIP FLOP module flipflop (D, CLK, Q); D CLK D FLIP FLOP Q Block Diagram Description of D Flip Flop input D, CLK; output reg Q; always @ (posedge CLK) begin Q <= D; end endmodule Verilog Description of D Flip Flop 42
BEHAVIOURAL DESCRIPTION OF 4-BIT REGISTER WITH WRITE ENABLE D 4 4 Wn REGISTER Clock Q Block Diagram Description of 4-Bit Register with Write Enable (Active Low) module reg4 (D, Wn, Clock, Q); input [3:] D; input Clock, Wn; output reg [3:] Q; always @ (posedge Clock) if (Wn==) Q <= D; else Q <= Q; endmodule Verilog Description of 4-Bit Register with Write Enable (Active Low) 43
4 D Q 4 Wn D FLIP FLOP CLK Drawing Description of 4-Bit Register with Write Enable (Active Low) module reg4 (D, Wn, Clock, Q); input [3:] D; input Clock, Wn; output reg [3:] Q; always @ (posedge Clock) if (Wn==) Q <= D; else Q <= Q; endmodule If the else condition is not specified, the complier will infer a latch circuit, and the resulting circuit may not be as expected 44
4-BIT REGISTER WITH SYNCHRONOUS RESETn D 4 4 Wn REGISTER Clock Q Rn module reg4 (D, Wn, Rn, Clock, Q); input [3:] D; input Clock, Wn, Rn; output reg [3:] Q; always @ (posedge Clock) if (Rn == ) Q <= 4 b; else if (Wn == ) Q <= D; else Q <= Q; endmodule Block Diagram Description of 4-Bit Register with Write Enable (Active Low) Verilog Description of 4-Bit Register with Write Enable and Reset (Active Low) 45
Description Level Comparison Behavioural module fulladder(x, y, Cin, S, Cout); input wire x, y, Cin; output reg S, Cout; always @ (x, y, Cin) begin S = x^y^cin; Cout = x&y (x^y) &Cin; end endmodule Functional module fulladder(x, y, Cin, s, Cout); input x, y, Cin; output s, Cout; assign s = ~x&~y&z ~x&y&~z x&~y&~z x&y&z; assign Cout = x&y x&cin y&cin; endmodule Structural module fulladder(x,y,cin,s,cout); input x, y, Cin; output s, Cout; wire w, w2, w3; xor(w, x, y); xor(s, w, Cin); and(w2, x, y); and(w3, w, Cin); or(cout, w2, w3); endmodule 46
KINDS OF ASSIGNMENTS IN PROCEDURAL STATEMENTS There are two kinds of assignments in procedural statements Blocking assignment statement Example: S = X + Y; Non-blocking assignment statement Example S <= X + Y; The = and <= differentiate between them 47
KINDS OF ASSIGNMENTS IN PROCEDURAL STATEMENTS Blocking assignment ( = ) S = X + Y; LSb = S[]; Statements are executed in order For each statement, the expression on the RHS is evaluated, and the result is transferred to the LHS before the next statement is executed Non-blocking assignment ( <= ) S <= X + Y; LSb <= S[]; RHS expressions of statements are executed in order After all RHS expressions are executed, then the assignments of values to the LHS are performed all at the same time Note that if a previous statement writes to a memory (eg, S <=X + Y), then that change will not be seen by subsequent statements which have the receiving variable as a source variable (eg, LSb <= S[]), due to propagation delay (See next 2 slides for an example) 48
If X = 4 b, Y = 4 b, S = 4 b, then after the following two lines are executed: S = X + Y; LSb = S[]; RESULT: S = 4 b LSb = If X = 4 b, Y = 4 b, S = 4 b, then after the following two lines are executed: S <= X + Y; LSb <= S[]; RESULT: S = 4 b LSb = 49
S <= X + Y; LSb <= S[]; ANALYSIS OF EXAMPLE NON-BLOCKING CASE X Y 4 4 4-BIT ADDER S 3 S S RHS Evaluation of S <= X + Y, time t t t t 2 t 2 RHS Evaluation of LSb <= S[], time t LSb CLK 3 LHS Assignments, time t 2 Note that during the posedge of CLK, the value input to S[] = will not have enough time to propagate to the input of LSb, and, therefore, the previous value of S[] = will be written into LSb S after posedge of CLK LSb after posedge of CLK 5
Previous example shows that S and LSb were implemented as registers As mentioned previously, when you declare a variable as type reg, that does not mean necessarily that the variable will be implemented in Verilog as a register However, even if S and LSb were not implemented as registers, the previous result and explanation still hold Now that we know the difference between blocking and nonblocking statements, the question is: when should we use blocking statements and when should we use non-blocking statements? We consider combinational and sequential circuits 5
Assignment Type for Sequential Logic Desired circuit to be described Example: 3-bit Shift Circuit: IN D Q Q D Q Q2 D Q Q 3 OUT CLK //Description : non-blocking always @ (posedge CLK) begin Q <=IN; Q 2 <=Q ; OUT<=Q 2 ; end //Description 2: blocking always @ (posedge CLK) begin Q =IN; Q 2 =Q ; OUT=Q 2 ; end Which assignment type should be used to truly describe the desired circuit? 52
Use Nonblocking for Sequential Logic always @ (posedge CLK) begin Q <=IN; Q 2 <=Q ; OUT<=Q 2 ; end Satisfies the Desired Circuit IN CLK D Q At the rising edge of CLK: The RHS of each line is evaluated When all RHS values have been evaluated, then they are transferred to their LHS variables, simultaneously This is equivalent to saying at the rising edge of CLK, the current values of the D inputs are transferred to their respective Q s Q D Q Q2 D Q Q 3 OUT Desired Circuit always @ (posedge CLK) begin Q =IN; Q 2 =Q ; OUT=Q 2 ; end IN CLK D Q OUT At the rising edge of CLK: Q =IN After that, Q 2 =Q =IN After that, OUT=Q 2 =Q =IN Equivalently, this is the generated circuit This is not the intended circuit General Rule: Use nonblocking assignments for sequential circuits 53
Assignment Type For Combinational Logic Desired circuit to be described Example: Combinational Circuit A B C X Y //Description always @ (A, B, C) begin X <= A & B; Y <= X C; end //Description 2 always @ (A, B, C) begin X = A & B; Y= X C; end Which assignment type should be used? 54
Use Blocking for Combinational Logic Example: Combinational Circuit Desired circuit to be described A X B C Y always @ (A, B, C) begin X <= A & B; Y <= X C; end When A, B, or C change: uses the old value of, and so will not get the desired value, which is, ie, the new as computed in the st line always @ (A, B, C) begin X = A & B; Y= X C; end When A, B, or C change: X = A AND B After that, Y = new value of X ORed with current value of C General Rule: Use blocking assignments for combinational circuits 55
[] S Brown and Z Vranesic, Fundamentals of Digital Logic with Verilog Design, New York: McGraw-Hill, 23 56