Development of a modern Airbag System Prototype COSIDE User Experience Dr. Thang Nguyen (Infineon Technologies Austria AG) SystemC AMS COSIDE User Group Meeting 2014
Agenda 1. Overview of Airbag System Application 2. Motivations 3. FPGA-based Development Framework 4. Accelerated System Co-Verification Framework 5. COSIDE Use Cases by IFAT 6. Real-life case study Page 2
Airbag System Application Overview & Challenges analogue Satellite Sensors (upfront & side impact, g-sensor, buckle switches...) Airbag SoC ASIC SPI_IF Embedded SW Main µc Airbag ECU analogue Airbag System Overview (Sensors <--> Controller <--> Actuators) Actuators (Squibs) Target System-under-Evaluation Sophisticated = Safety Critical Realtime Embedded (SW/FW) Mixed-Signal Cost-Reduction = high integration challenges in verification effort Main µc On-Board Sensors SPI_IF SPI HW SPI HW Safing_Engine (SE) SE - Digital CORE (RTL) Digital CORE (RTL) FW SMPS_Dig and LVRs_Dig (RTL) A/D_IF SE_AFE Model Supply_net Module Reg_IF Module Digital Logic Sub-System Digital (RTL) Supply_net CENTRAL_Dig (RTL) SMPS Modules (Buck/ Boost Converter) reset SoC Power Supply Models SoC_PWR ipsg sys_clk A/D_IF CENTRAL_AFE (Diagnostic and Monitoring) Model Supply_net LVRs ilvrs SQB_Driver x Loops HS&LS Sensor_IF (PSI or DSI) Watchdog Modules AFE Digital Toplevel Airbag SoC Chipset TL Architecture Voltage Measurement GPA-IO PWR_Train IF (CAN/LIN) Page 3
Motivations Late bugs are expensive!! Rapid Prototyping (Emulation) can help! Interactive Concept Development Support test scenario where SIM is impractical Early (before Integration&Test) Concept Verification System Validation 2014-01-0240 4
FPGA-based Development Workflow Ref: Nguyen.T (IFAT) et. Wooters.S (TRW), SAE 2014 "FPGA-Based Development for Sophisticated Automotive Embedded Safety Critical System" Page 5
Advantages of FPGA-based SoC Emulation System Page 6
DUT Implementations Test Environment Accelerated System Co-Verification Framework Simulation based Environment HIL based Tester UVM-SystemC Environment re-use UVM-SystemC Environment Driver Monitor Driver Monitor Design Sign-Off DUT SystemC (behavioral) DUT Mixed Abstraction DUT-FPGA Prototype DUT-ASIC Silicon Abstraction level Verification Lab Validation Ref: Nguyen.T (IFAT) et. P.Erhlich, T.Vörtler (FhG), DVCON Europe 2014 "UVM-SystemC based HIL-Simulations for accelerated System Co-Verification" Highlights: Acceleration of verification activity, including scenarios which are impractical for simulation Reuse Link between Pre-SI and Lab Evaluation Cost-effective HIL-based tester, e.g.: Zedboard vs. dspace UVM Layering concept Page 7
Use Cases by IFAT 1. FPGA Toplevel Integration and Front-End Design especially, Analog Functional Stub Modeling 2. Supporting FPGA Back-End Implementation a) Scripting for Xilinx ISE for System HW realization b) Data2Mem scripting for System Firmware update 3. Verification & Lab Validation of the Prototype a) Test Scenarios Development b) Test Stimulus Development and Validation c) Test Bench Generation and Test execution (@ SIM & physical HW) d) SIM root-cause analysis and bug-fix testing support Page 8
Case study: Real-life Airbag SoC Sensor IF Paremetric testing of AFE circuit implementation Workstation with StubFnc Ctrl Software RS232 /RJ-45 Airbag_AFE StubFunC FPGA_SoC_TOP FPGA Mother Board TC_Board init_sync Main µc/spi Emulator SPI_IF SPI HW IF Airbag_Dig Sensor TxR logic (DUT1) Ext_DataX_ IF 12/24/36MhZ Ext_DataX_ IF AFE Analogue TC (DUT2) Vdsi_X (X=1..6) DSI3 Sensor DSI3 Emulyzer/Real Sensor DSI3 Emulyzer/Real Sensor DSI/PSI Emulyzer/Real Sensor Emulyzer/Real HIL_Tester, e.g.: Zedboard with the reuse of UVM- SystemC TB Testing/evaluating the new implementation of sensor TxR Trans_ctrl Page 9
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