Wht do ll those bits men now? bits (...) Number Systems nd Arithmetic or Computers go to elementry school instruction R-formt I-formt... integer dt number text chrs... floting point signed unsigned single precision double precision............ Questions About Numbers How do you represent negtive numbers? frctions? relly lrge numbers? relly smll numbers? How do you do rithmetic? identify errors (e.g. overflow)? Wht is n nd wht does it look like? =rithmetic logic unit Introduction to Binry Numbers Consider 4-bit binry number Deciml Binry Deciml Binry 4 5 6 7 Exmples of binry rithmetic: = 5 = 6
Negtive Numbers? Some Alterntives We would like number system tht provides obvious representtion of,,... uses dder for ddition single vlue of equl coverge of positive nd negtive numbers esy detection of sign esy negtion Sign Mgnitude -- MSB is sign bit, rest the sme - == -5 == One s complement -- flip ll bits to negte - == -5 == Two s Complement Representtion s complement representtion of negtive numbers Tke the bitwise inverse nd dd Biggest 4-bit Binry Number: 7 Smllest 4-bit Binry Number: -8 Deciml -8-7 -5 - - - 4 5 6 7 Two s Complement Binry Two s Complement Arithmetic Deciml s Complement Binry Deciml s Complement Binry - - - 4-5 5 6-7 7-8 Exmples: 7-6 = 7 (- 6) = - 5 = (- 5) = -
Some Things We Wnt To Know About Our Number System Detection negtion sign extension =>,, - =>,, overflow detection 5 6 5 7 - -5 7 So how do we detect overflow? Instruction Fetch Instruction Decode Opernd Fetch Execute Store Next Instruction Arithmetic -- The hert of instruction execution b opertion result Designing n Arithmetic Logic Unit A B N N op Control Lines (op) Function And Or Add Subtrct Set-on-less-thn N Zero
A One Bit -bit A -bit -bit This -bit will perform AND, OR, nd ADD b b - b b b b How About Subtrction? Keep in mind the following: (A - B) is the sme s: A (-B) s Complement negte: Tke the inverse of every bit nd dd Bit-wise inverse of B is!b: A - B = A (-B) = A (!B ) = A!B b Binvert Detection Logic Crry into MSB! = Crry out of MSB For N-bit : = [N - ] XOR [N - ] A B A B A B A B -bit -bit -bit -bit X Y X XOR Y
Zero Detection Logic Zero Detection Logic is just one BIG NOR gte Any non-zero input to the NOR gte will cuse its output to be zero Set-on-less-thn A B A B A B A B -bit -bit -bit -bit Do subtrct use sign bit route to bit of result ll other bits zero Binvert b. Binvert b detection b. Set Binvert b b b b Full Bnegte b b b b Set Set wht signls ccomplish: neg oper dd? sub? nd? Zero or? beq? slt? The Disdvntge of Ripple Crry The dder we just built is clled Ripple Crry Adder The crry bit my hve to propgte from LSB to MSB Worst cse dely for n N-bit RC dder: N-gte dely A -bit B A -bit B A -bit B A -bit B A B sign bit (dder output from bit ) The point -> ripple crry dders re slow. Fster ddition schemes re possible tht ccelerte the movement of the crry from one end to the other.
MULTIPLY Pper nd pencil exmple: Multiplicnd Multiplier x MULTIPLY HARDWARE Version 64-bit Multiplicnd reg, 64-bit, 64-bit Product reg, -bit multiplier reg Multiplicnd Shift left Product =? m bits x n bits = mn bit product Binry mkes it esy: => plce ( x multiplicnd) => plce multiplicnd ( x multiplicnd) we ll look t couple of versions of multipliction hrdwre 64-bit Product Write Control test Multiplier Shift right bits Multiply Algorithm Version Multiplier Multiplicnd Product Multiplier =. Add multiplicnd to product nd plce the result in Product register Strt. Test Multiplier. Shift the Multiplicnd register left bit. Shift the Multiplier register right bit nd repetition? Multiplier = No: < repetitions Observtions on Multiply Version clock per cycle => clocks per multiply Rtio of multiply to dd : / bits in multiplicnd lwys => 64-bit dder is wsted s inserted in left of multiplicnd s shifted => lest significnt bits of product never chnged once formed Insted of shifting multiplicnd to left, shift product to right? Wsted spce (zeroes) in product register exctly mtches meningful bits of multiplier t ll times. Combine? Yes: repetitions Done
MULTIPLY HARDWARE Version -bit Multiplicnd reg, -bit, 64-bit Product reg, (-bit Multiplier reg) -bit Multiplicnd bits Product Shift right Write Multiplicnd Product Control test Product =. Add multiplicnd to the left hlf of the product nd plce the result in the left hlf of the Product register Strt. Test Product. Shift the Product register right bit nd repetition? Done Product = No: < repetitions Yes: repetitions Observtions on Multiply Version steps per bit becuse Multiplier & Product combined -bit dder MIPS registers Hi nd Lo re left nd right hlf of Product Gives us MIPS instruction MultU Wht bout signed multipliction? esiest solution is to mke both positive & remember whether to complement product when done. Divide: Pper & Pencil DIVIDE HARDWARE Version Divisor Quotient Dividend 64-bit Divisor reg, 64-bit, 64-bit Reminder reg, -bit Quotient reg Divisor Shift right Reminder See how big number cn be subtrcted, creting quotient bit on ech step Binry => * divisor or * divisor Dividend = Quotient x Divisor Reminder 64-bit Reminder Write Control test Quotient Shift left bits
Divide Algorithm Version Tkes n steps for n-bit Quotient & Rem. Quotient Divisor Reminder Reminder >= Strt. Subtrct the Divisor register from the Reminder register, nd plce the result in the Reminder register. Test Reminder Reminder < DIVIDE HARDWARE Version -bit Divisor reg, -bit, 64-bit Reminder reg, (-bit Quotient reg) Divisor Strt. Shift the Reminder register left bit. Subtrct the Divisor register from the left hlf of the Reminder register nd plce the result in the left hlf of the Reminder register. Shift the Quotient register to the left setting the new rightmost bit to.. Shift the Divisor register right bit. rd repetition? b. Restore the originl vlue by dding the Divisor register to the Reminder register, nd plce the sum in the Reminder register. Also shift the Quotient register to the left, setting the new lest significnt bit to. No: < repetitions bits -bit Reminder Shift right Shift left Write Control test Reminder > Reminder < Test Reminder. Shift the Reminder register to the b. Restore the originl vlue by dding left, setting the new rightmost bit to the Divisor register to the left hlf of the Reminder register nd plce the sum in the left hlf of the Reminder register. Also shift the Reminder register to the left, setting the new rightmost bit to No: < repetitions nd repetition? Yes: repetitions Yes: repetitions Done. Shift left hlf of Reminder right bit Done Observtions on Divide Version Sme Hrdwre s Multiply: just need to dd or subtrct, nd 6-bit register to shift left or shift right Hi nd Lo registers in MIPS combine to ct s 64-bit register for multiply nd divide Signed Divides: Simplest is to remember signs, mke positive, nd complement quotient nd reminder if necessry Note: Dividend nd Reminder must hve sme sign Note: Quotient negted if Divisor sign & Dividend sign disgree Key Points Instruction Set drives the design performnce, CPU clock speed driven by dder dely Multipliction nd division tke much longer thn ddition, requiring multiple ddition steps.