Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care
Standard Logic Std_ulogic is an unresolved data type; only 1 driver. Std_logic is a resolved data type; > than 1driver. Both have the same nine states. Both have a vector form: std_ulogic_vector, std_logic vector Both are contained in a package called standard_logic_1164 In MAX+PLUS II, std_logic must have only 1 driver to synthesize.
Using Standard Logic To use standard logic, define the library, define the package in the library, define the objects in the package library list_library_names; use library.package.object; library IEEE; use IEEE.Std_Logic_1164.all;
Using Standard Logic Objects of type std_logic can be assigned to objects of type std_ulogic, and vice-versa. For MAX+PLUS, only resolved logic can be synthesized so both logic types behave the same way in terms of drivers. There are other standards which use std_logic so this is typically preferred.
Concurrent Assignments Concurrent statements: execute in parallel (at the same time), behaviour is independent of the order in which they are written X <= A or B; Z<= C or X; Z <= C or X; X <= A or B; Remember the statements represent hardware!
Concurrent Assignments Consider X <= X + Y; In software, X and Y are registers. In hardware, X and Y are signals. Code describes an adder, with no implied storage registers. Describes feedback around combinational logic. Think hardware!
Sequential Assignments Sequential statements are only found within a process. The process is not a fundamental design unit. The process must be contained within an architecture.
The Process MUX: process (A,B,SEL) begin if SEL = '1' then Z <= A; else Z <= B; end if; end process MUX;
The Process A process is invoked when one of the signals in its sensitivity list has an event, i.e. changes value. Each process executes its statements in sequence. Multiple processes interact with each other concurrently.
The Process architecture A of E is begin -- concurrent statements P1 : process begin -- sequential statements end process P1; -- concurrent statements P2 : process begin -- sequential statements end process P2; -- concurrent statements end A;
Concurrent vs Sequential Consider: Z <= A and B; Z <= C and D; architecture CONCURRENT of MULTIPLE is signal Z, A, B, C, D : std_logic; begin Z <= A and B; Z <= C and D; end CONCURRENT;
Concurrent vs Sequential architecture SEQUENTIAL of MULTIPLE is signal Z, A, B, C, D : std_logic; begin process (A, B, C, D) begin Z <= A and B; Z <= C and D; end process; end SEQUENTIAL;
Process Execution Signals assigned within a process are not actually updated until the process suspends execution, i.e. after the last sequential statement Ensures that the signal update is clean. For previous example, Z is never updated with the value of A and B.
Sensitivity List MUX: process (A, B, SEL) begin if SEL = '1' then Z <= A; else Z <= B; end if; end process MUX;
MUX: process (A, B) begin if SEL = '1' then Z <= A; else Z <= B; end if; end process MUX; Sensitivity List
Combinational Logic If describing combinational logic in a process, the sensitivity list should always be complete. A complete sensitivity list contains every signal that could be considered an input.
The Process Program flow within the process is determined by: the case statement the for loop the if statement These statements only make sense within sequential code and, therefore, are only valid within a process.
If Statement If condition then -- sequential statements end if; If condition then -- sequential statements else -- sequential statements end if;
If-Elsif Statement if condition then -- sequential statements elsif condition then -- sequential statements elsif condition then -- sequential statements else -- sequential statements end if;
If-Elsif Statement process (A, B, C, X) begin if (X = "0000") then Z <= A; elsif (X <= "0101") then Z <= B; else Z <= C; end if; end process;
Case Statement case OBJECT is when VALUE_1 => -- statements when VALUE_2 => -- statements when VALUE_3 => --statements --etc... end case;
process (A, B, C, X) begin case X is when 0 to 4 => Z <= B; when 5 => Z <= C; when 7 9 => Z <= A; when others => Z <= 0; end case; end process; Case Statement
Case Statement The object may be any valid expression. Values may be specified: individually by range, e.g. 0 to 4 by list, e.g. 7 9 by others clause covers all other possible values that have not been specified
Case Statement Values must be: constant values of the same type as object specified only once. All possible values must be specified explicitly or with the others clause.
For Loop for index in range loop -- sequential statements end loop; for I in 0 to 3 loop -- statements end loop;
For Loop The index does not have to be declared. The range must be fixed to allow the synthesis tool to unfold the loop. Logic inside the loop is replicated, once for each loop, and then the circuit is optimized.
entity EX is port (A : in std_logic_vector(0 to 15); SEL : in integer range 0 to 15; Z : out std_logic); end EX; architecture RTL of EX is begin WHAT: process (A, SEL) begin for I in 0 to 15 loop if SEL = I then Z <= A(I); end if; end loop; end process WHAT; end RTL;
Important Trivia Not case sensitive Ignores spaces and line breaks Comments begin with -- and end at the end of the line. Many reserved words Strongly typed language value assigned to a signal or variable must match exactly in type
Important Trivia Identifiers (variable and signal names) start with a character may contain letters, numbers, _(underscore) may not contain, may not end with _ VHDL code is contained in text files with file name name.vhd File name must be the same as entity name