EECS150 Lab Lecture 2 Design Verification

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EECS150 Lab Lecture 2 Design Verification Vincent Lee Electrical Engineering and Computer Sciences University of California, Berkeley 9/7/2012 EECS150-Fa12-lab1 1

Lab Logistics T minus three weeks-ish until the project starts We re getting closer to Dan Garcia s hand of God For this lab, you will not be synthesizing your design = not using FPGA Grades for Lab 0 have been uploaded to bspace so check to make sure you have a score Labs are due by the last lab section of the week after they are assigned 9/7/2012 EECS150-Fa12-lab1 2

Agenda Testing Methodologies What we forgot to cover last week Xilinx Report Tools and Design Flow: Where are we? Software Simulation and Navigating Modelsim This Week s Lab: ALU and verification Parsing Register Transfer Level (RTL) Descriptions Tips, Tricks, Miscellaneous Things to Know 9/7/2012 EECS150-Fa12-lab1 3

The Xilinx Report Generator We tried to go over this with everyone after check off Xilinx will generate a report file every time you try to run synthesis to bit stream generation Can open the report by running make report command from same path as Makefile Contains resource utilization, timing information, and more Also displays list of errors and/or warnings 9/7/2012 EECS150-Fa12-lab1 4

Xilinx Report 9/7/2012 EECS150-Fa12-lab1 5

Errors, Warnings, Infos 9/7/2012 EECS150-Fa12-lab1 6

A Note on Errors and Warning Errors are bad Fix them Warnings Some generated by Xilinx tools nothing you can do about it Can be generated by your HDL code may or may not need to be fixed Good practice to always check for warnings coming from you code Don t always have to fix but May give hints as to why your synthesized design isn t working There s usually a reason why the tools are complaining about your code 9/7/2012 EECS150-Fa12-lab1 7

Testing Methodologies Exhaustive testing Throw every possible input at the circuit (for CL anyways) Ideal and covers everything including edge cases (100% coverage) Scales very poorly Random testing Uniform sampling of input space Edge cases randomly sampled (limited coverage) Scales better than exhaustive testing May combine with some target vectors 9/7/2012 EECS150-Fa12-lab1 8

Testing Methodologies Button-up approach Unit test most primitive modules first Work your way up by running integration tests when modules interact with each other For complex systems, very effective verification method Top-down approach Start at top level module and work your way down through submodules Stub modules that aren t implemented Good if problems tend to occur towards top 9/7/2012 EECS150-Fa12-lab1 9

For this lab and class Recommend button-up approach Project will have many small modules that compose a very large complex system Single bug will cripple your project Random testing for ALU and system with many inputs Supplement hardcoded test vectors to cover edge cases and frequently used cases 9/7/2012 EECS150-Fa12-lab1 10

For this lab and class We will only provide basic test cases Your job to fill in the gaps the real world is 50%+ testing and 50%- everything else In general, groups who write more/most test cases finish the project faster Don t count on us giving you a solution if you fall behind You need to understand your code to do the next checkpoint We cannot write testbenches for modules that you designed 9/7/2012 EECS150-Fa12-lab1 11

Digital Design Development Cycle 9/7/2012 EECS150-Fa12-lab1 12

Where We Are in the Development Flow 9/7/2012 EECS150-Fa12-lab1 13

Software Simulation Tool that simulates behavior of HDL code before synthesis Gives design feedback as waveforms or test messages Requires explicit simulation test cases which usually aren t synthesized Sometimes may differ from actual synthesis since tools infer logic upon synthesis Hopefully irons out most/all bugs before synthesis 9/7/2012 EECS150-Fa12-lab1 14

Motivation Behind Software Simulation Synthesis takes FOREVER want to be able to do verification quickly in software Enhances visibility by allowing access to every signal Testing is important A broken product isn t worth anything (also not worth credit) Entire teams in industry devoted to verification and DFT Systems are complicated Easy to make mistake in 1000s to millions of lines of code Modules may work separately but not together NRE costs are expensive one bug can cost the entire design 9/7/2012 EECS150-Fa12-lab1 15

Modelsim Simulation Tool 9/7/2012 EECS150-Fa12-lab1 16

Navigating the Tools Modelsim can be invoked by the vsim command Waveform colors Green waveforms usually good (all values defined) Red waveforms usually bad (undefined values) Blue waveforms usually bad (undriven values) Radix (hex, decimal, etc.) Right click signal -> Radix -> Selected Radix 9/7/2012 EECS150-Fa12-lab1 17

Navigating the Tools Use + or - to zoom in or out Toggling leafs on and off - removes excess file path description 9/7/2012 EECS150-Fa12-lab1 18

This Week s Lab Objectives: Become familiar with module test harnesses and testbenches Learn how to use Modelsim to simulate in software and debug your modules before synthesis Pre-lab requirements: Write verilog for ALU before lab Check off requirements: Functional ALU and testbenches Answers to checkoff questions Due Thursday 9/20 @ 8PM 9/7/2012 EECS150-Fa12-lab1 19

This Week s Lab You will be provided the skeletal files for: ALU testbench (ALUTestbench.v) ALU test vector harness (ALUTestVectorTestbench.v) ALU Decoder (ALUdec.v) ALU file (ALU.v) You will NOT be synthesizing the design (no makefile on top level) Instead you will be verifying your design by using Modelsim (makefile in /sim directory) READ THE DOCUMENT AND RTL SPECIFICATION 9/7/2012 EECS150-Fa12-lab1 20

ALU Decoder and ALU Controller for the ALU Takes instruction Opcode and Func Deduces appropriate ALUOp ALU Takes ALUOp and operands Performs operation specified on operands 9/7/2012 EECS150-Fa12-lab1 21

ALU Decoder and ALU Simulation Test Harness ALU Decoder and ALU are Devices Under Test (DUTs) Equivalent block diagram for simulation: 9/7/2012 EECS150-Fa12-lab1 22

Register Transfer Level (RTL) Descriptions SEXT(*) = sign extend value of * ZEXT(*) = zero extend value of * PC = memory address of instruction >>> = shift right arithmetic (A? B : C) = if A, then evaluate to B, else evaluate to C BMEM(*) = byte memory at * HMEM(*) = half memory at * WMEM(*) = word memory at * 9/7/2012 EECS150-Fa12-lab1 23

RTL Example: Load Byte (I-Type) 9/7/2012 EECS150-Fa12-lab1 24

RTL Example: Branch on Less Than or Equal (J-Type) 9/7/2012 EECS150-Fa12-lab1 25

Lab Tips and Tricks Read the lab document and understand the specification before you start Watch for signed and unsigned operations they are different Unsigned comparisons Unsigned loads Watch source field ordering order is important Watch order for SLLV, SRLV, and SRAV R[$rt] >> R[$rs] vs. R[$rs] << R[$rt] This will make your ALU fail the testbench Shift right logical (SRL) and shift right arithmetic (SRA) are different Watch operation binding strength 9/7/2012 EECS150-Fa12-lab1 26

Running Simulation To run simulation, cd to /sim directory Run make in directory Simulation output will fill the screen for each testbench you are running Simulator looks in /sim/tests for.do files each file specifies one test case simulation Simulation generates /results directory with transcript and waveform file (.wlf) Waveform can be viewed with Modelsim or calling./viewwave 9/7/2012 EECS150-Fa12-lab1 27

Macro Files Macro files help define variables so that you don t have to hardcode: Indicated by.vh file Use macros in verilog by using tick mark ` Two macro files included in /src directory ALUop.vh contains ALU operation code macros Opcode.vh contains MIPS ISA opcode macros 9/7/2012 EECS150-Fa12-lab1 28

Lab Assignment Prelab assignment: Write code for ALU and ALU decoder Lab assignment: Complete testbenches and add appropriate test cases Write hardcoded tests and manually add testcases to file Yes we want you to type in the 1s and 0s to the testvector file Simulate and verify that ALU and decoder works correctly Checkoff Demonstrate functional ALU and ALU Decoder 9/7/2012 EECS150-Fa12-lab1 29

Next Week s Lab Next week s lab lecture: Overview of Chipscope Next week s lab: List Processor and Chipscope Datapath and Controller Design What to do when simulation works but synthesis fails oh dear 9/7/2012 EECS150-Fa12-lab1 30

Questions, comments, or concerns? 9/7/2012 EECS150-Fa12-lab1 31

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