Formal Contribution towards Coverage Closure. Deepak Pant May 2013

Similar documents
Next Generation Verification Process for Automotive and Mobile Designs with MIPI CSI-2 SM Interface

IOT is IOMSLPT for Verification Engineers

Incisive Enterprise Verifier

Yafit Snir Arindam Guha Cadence Design Systems, Inc. Accelerating System level Verification of SOC Designs with MIPI Interfaces

The How To s of Metric Driven Verification to Maximize Productivity

Will Everything Start To Look Like An SoC?

Tackling Verification Challenges with Interconnect Validation Tool

Incisive Coverage Introduction and RAK Overview

Practical experience in automatic functional coverage convergence and reusable collection infrastructure in UVM verification

Qualification of Verification Environments Using Formal Techniques

Stacking UVCs Methodology. Revision 1.2

Making it Easy to Deploy the UVM by Dr. Christoph Sühnel, frobas GmbH

UVM-SystemC Standardization Status and Latest Developments

FPGA chip verification using UVM

Samsung and Cadence. Byeong Min, Master of Infrastructure Design Center, System LSI Business, Samsung. The Customer. The Challenge. Business Challenge

Verification Planning with Questa Verification Management

Will Everything Start To Look Like An SoC?

width: 10, 20 or 40-bit interface maximum number of lanes in any direction

Portable Stimulus vs Formal vs UVM A Comparative Analysis of Verification Methodologies Throughout the Life of an IP Block

Advanced Verification Topics. Bishnupriya Bhattacharya John Decker Gary Hall Nick Heaton Yaron Kashai Neyaz Khan Zeev Kirshenbaum Efrat Shneydor

Contents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)

Verification Futures The next three years. February 2015 Nick Heaton, Distinguished Engineer

A Systematic Approach to Creating Behavioral Models CDNLive, March, 2015 Bob Peruzzi, Joe Medero

Universal Verification Methodology (UVM) Module 5

A comprehensive approach to scalable framework for both vertical and horizontal reuse in UVM verification

Automating Root-Cause Analysis to Reduce Time to Find Bugs by Up to 50%

Maximizing Verification Effectiveness Using MDV

DDR SDRAM Bus Monitoring using Mentor Verification IP by Nikhil Jain, Mentor Graphics

An approach to accelerate UVM based verification environment

Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog. Paradigm Works, Inc. Dr.

Cypress Adopts Questa Formal Apps to Create Pristine IP

Verification Futures Nick Heaton, Distinguished Engineer, Cadence Design Systems

SPECMAN-E TESTBENCH. Al. GROSU 1 M. CARP 2

Graph-Based Verification in a UVM Environment

DO-254 Testing of High Speed FPGA Interfaces by Nir Weintroub, CEO, and Sani Jabsheh, Verisense

An Introduction to the Unified Coverage Interoperability Standard UCIS Technical Committee

Responding to TAT Improvement Challenge through Testbench Configurability and Re-use

Maximize Vertical Reuse, Building Module to System Verification Environments with UVMe

Complex Low Power Verification Challenges in NextGen SoCs : Taming the Beast!

Efficient Verification of Mixed-Signal SerDes IP Using UVM

Portable VHDL Testbench Automation with Intelligent Testbench Automation by Matthew Ballance, Mentor Graphics

Ensuring System Integrity through Advanced System Software Verification

Is Power State Table Golden?

Modular SystemVerilog

FPGA Verification How to improve verification without throwing everything away

Software Driven Verification at SoC Level. Perspec System Verifier Overview

Leveraging Formal Verification Throughout the Entire Design Cycle

Reuse MATLAB Functions and Simulink Models in UVM Environments with Automatic SystemVerilog DPI Component Generation

Making the Most of your MATLAB Models to Improve Verification

UVM in System C based verification

VERIFICATION OF RISC-V PROCESSOR USING UVM TESTBENCH

Intelligent Coverage Driven, modern verification for VHDL based designs in native VHDL with OSVVM

Design and Verification of Slave Block in Ethernet Management Interface using UVM

Embedded Hardware and Software

Fault Injection & Formal Made for Each Other

Complex Signal Processing Verification under DO-254 Constraints by François Cerisier, AEDVICES Consulting

Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide by Prashant Dixit, Questa VIP Product Team, Mentor Graphics

Vertical Reuse of functional verification from subsystem to SoC level (with seamless SoC emulation)

Compatible Qualification Metrics for Formal Property Checking

Verification and Validation Introducing Simulink Design Verifier

Fast Track to Productivity Using Questa Verification IP by David Aerne and Ankur Jain, Verification Technologists, Mentor Graphics

Mixed Signal Verification Transistor to SoC

Course Profile Assertions in UVM

VCS AMS. Mixed-Signal Verification Solution. Overview. testing with transistor-level accuracy. Introduction. Performance. Multicore Technology

Verification at ARM. Overview. Alan Hunter

Reducing the cost of FPGA/ASIC Verification with MATLAB and Simulink

ASIC world. Start Specification Design Verification Layout Validation Finish

verification in hardware (ASIC/FPGA) Sadat Rahman ( ) Digital ASIC & FPGA Design Ericsson Lund,

6 Month Certificate Program in VLSI Design & Verification" with Industry Level Projects. Tevatron Technologies Prívate Limited

Beyond Soft IP Quality to Predictable Soft IP Reuse TSMC 2013 Open Innovation Platform Presented at Ecosystem Forum, 2013

Verification of Cache Coherency Formal Test Generation

INDUSTRIAL TRAINING: 6 MONTHS PROGRAM TEVATRON TECHNOLOGIES PVT LTD

UVM for VHDL. Fast-track Verilog for VHDL Users. Cont.

Verification Prowess with the UVM Harness

PG DIPLOMA COURSE IN VERIFICATION USING SYSTEMVERILOG & UVM NEOSCHIP TECHNOLOGIES

Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS

UVM BASED TEST BENCH TO VERIFY AMBA AXI4 SLAVE PROTOCOL

Test and Verification Solutions. ARM Based SOC Design and Verification

NetSpeed ORION: A New Approach to Design On-chip Interconnects. August 26 th, 2013

Hardware Design and Simulation for Verification

Verifying big.little using the Palladium XP. Deepak Venkatesan Murtaza Johar ARM India

LEVERAGING A NEW PORTABLE STIMULUS APPROACH Graph or rule based stimulus descriptions

UVM Ready: Transitioning Mixed-Signal Verification Environments to Universal Verification Methodology

Development of UVM based Reusabe Verification Environment for SHA-3 Cryptographic Core

Verification of Digital Systems, Spring UVM Basics

CHALLENGES OF TODAY'S COMPLEX SOC: PERFORMANCE VERIFICATION PANKAJ SINGH, MALATHI CHIKKANNA

ISO26262 This Changes Everything!

International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.6, December

Verification at ARM. Overview 1/18/18

Génération de tests basés sur les modèles pour des systèmes sur puce avec cohérence de caches

Power: What s the problem?

Veloce2 the Enterprise Verification Platform. Simon Chen Emulation Business Development Director Mentor Graphics

Configuring a Date with a Model

Complex Low Power Verification Challenges in NextGen SoCs: Taming the Beast!

Practical Experience in Automatic Functional Coverage Convergence and Reusable Collection Infrastructure in UVM

Next Generation Design and Verification Today UVM REG: Path Towards Coverage Automation in AMS Simulations

Stitching UVM Testbenches into Integration-Level

SoC Verification Methodology. Prof. Chien-Nan Liu TEL: ext:

Hardware Design Verification: Simulation and Formal Method-Based Approaches William K Lam Prentice Hall Modern Semiconductor Design Series

SoC / ASIC / FPGA / IP

Transcription:

Formal Contribution towards Coverage Closure Deepak Pant May 2013

Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary 2 2012 Cadence Design Systems, Inc. All Rights Reserved

Incisive Metric-Driven Verification (MDV) Use Enterprise Planner to bind assertions and checks goals to features; generate the vplan Spec Design Specification Plan Write new assertions, or use Assertion Based VIP Measure / Analyze Construct output_ready:assert property Execute Contributions from multiple technologies shown in a unified view IFV/IEV IES-XL IFV IFV IFV HW IFV Run formal or dynamic assertions in parallel Unicov Unicov Unicov Database Database Database UniCov DB 3 2012 Cadence Design Systems, Inc. All Rights Reserved Unicov Unicov Unicov Database Database Database UniCov DB Unicov Unicov Unicov Database Database Database UniCov DB

Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary 4 2012 Cadence Design Systems, Inc. All Rights Reserved

System Integrator Verification Engineer Designer Verification Apps Across the Project Life Cycle RTL Design Testbench Development RTL Refinement IP Verification Integration Project Start RTL partially available Testbench Ready Feature/Protocol Finished Verification Closure System Tapeout Super Linting Protocol Compliance Coverage Unreachability Analysis Register Map Validation SoC Connectivity 5 2012 Cadence Design Systems, Inc. All Rights Reserved

The Dead Code Challenge module multiplexor4_1 (out, in1, in2, in3, in4, cntrl1, cntrl2); output out; input in1, in2, in3, in4, cntrl1, cntrl2; reg out; always @(in1 or in2 or in3 or in4 or cntrl1 or cntrl2) case ({cntrl1, cntrl2}) 2'b00 : out = in1; 2'b01 : out = in2; 2'b10 : out = in3; 2 lines are uncovered 2'b11 : out = in4; default : $display("please check control bits"); endcase endmodule Question: Is the uncovered code reachable or unreachable? Test suite is insufficient. BAD! Fix RTL or discard hole. OK! 6 2012 Cadence Design Systems, Inc. All Rights Reserved

The Coverage Hole Problem Design & Testbench Simulation Coverage Database Run simulation and collect metrics Review metrics in IMC Uncovered items Create more tests! Question: Is the uncovered item reachable or unreachable? 7 2012 Cadence Design Systems, Inc. All Rights Reserved

Coverage Unreachability App Overview Fully Automated! Design & Testbench Simulation Regression Incisive Enterprise Verifer Holes N Unreachable? Y Coverage Database no action Merge Unreachable Coverage Database Leverage formal to determine if holes are reachable Block code coverage Expression code coverage But: automated flow no formal/abv knowledge required! And: Independent of testbench methodology! 8 2012 Cadence Design Systems, Inc. All Rights Reserved

Results Handling Fully Automated! Design & Testbench Simulation Regression Incisive Enterprise Verifer Holes N Y Unreachable? Coverage Database no action Merge Unreachable Coverage Database Only unreachable holes are reported Merge unreachable database into original simulation database 9 2012 Cadence Design Systems, Inc. All Rights Reserved

Result Reviewing Focus your effort Fully here Automated! Exclude Design & Testbench UNR Simulation Regression Incisive Enterprise Verifer Holes 100% N Y Unreachable? Exclude Coverage Database no action Merge Unreachable Coverage Database Read in merged database (simulation + unreachable) User to accept UNR by converting into Exclude RESULT: Enhanced code coverage as elements found to be unreachable are now annotated as Exclude 10 2012 Cadence Design Systems, Inc. All Rights Reserved

Customer Feedback Successful adoption at multiple customers Feedback and impressions Easy to use Good performance Saves a lot of review cycles for hole analysis Tech. paper: Freescale Bangalore at CDNLive! India http://www.cadence.com/cdnlive/in/2011/pages/proceedingssum mary.aspx > I. Silicon Realization: Functional Verification > Session 1.6 : Innovative Approach To Coverage Closure Through Unreachability Analysis Flow 11 2012 Cadence Design Systems, Inc. All Rights Reserved

Fujitsu Article in EETimes http://www.eetimes.com/design/automotive-design/4390825/using-code-coverageanalysis-to-verify-2d-graphic-engines-in-automotive-apps?pagenumber=0 12 2012 Cadence Design Systems, Inc. All Rights Reserved

Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary 13 2012 Cadence Design Systems, Inc. All Rights Reserved

Enriched Metrics Incisive Enterprise Verifier Dynamic Simulation Formal Engines Formal & Dynamic sim results automatically annotated to the vplan Verify formal assumptions Highlight unreachability Take credit for formal work 14 2012 Cadence Design Systems, Inc. All Rights Reserved

Report Functional Unreachables Simulation coverage hole But can it be reached!?!? Formal says NO! 15 2012 Cadence Design Systems, Inc. All Rights Reserved

UVM + IEV = Multi-Engine UVM Module UVC Scoreboard Coverage UVM Testbench DUT I/F UVC Mon Mon VC3 CPU Mem BFM BFM SEQR Mon DRV A A SV Interface Create Passive Test Replay all formal witnesses in the PASSIVE UVM environment Formal contributes Scoreboard failures Covergroup filling Code coverage Etc Virtual Sequencer A Periph SV Interface Mon Mon Mon A BFM BFM DRV Periph A SV Interface Mon Mon Mon BFM BFM DRV Bring results together using EMGR SEQR SEQR Protocol1 VC3 UVC Protocol2 VC3 UVC 16 16 2012 Cadence Design Systems, Inc. All Rights Reserved

Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary 17 2012 Cadence Design Systems, Inc. All Rights Reserved

Summary The Coverage Unreachability App automates post-simulation coverage hole analysis TB and DUT independent Minimal tool knowledge is required Reduces time to verification closure Unreachables can be analyzed or removed from the master RTL/coverage database Easy to setup, quick to run, increases overall productvity Formal MDV & Coverage Unreachability a key tool for Coverage Closure Bottom Line Formal MDV & Coverage Unreachability a key tool for Coverage Closure 18 2012 Cadence Design Systems, Inc. All Rights Reserved

Documentation and Webinars Incisive Enterprise Verifier User Guide Chapter 5: Analyzing Unreachable Coverage <root>/doc/ievuser/ievuser.pdf Archived webinars http://www.cadence.com/fv_webinars Formal Apps to Automate Mainstream Verification Challenges What to Do When Code Coverage Closure Seems Impossible 19 2012 Cadence Design Systems, Inc. All Rights Reserved

20 2012 Cadence Design Systems, Inc. All Rights Reserved