Ultra-thin Capacitors for Enabling Miniaturized IoT Applications Fraunhofer Demo Day, Oct 8 th, 2015 Konrad Seidel, Fraunhofer IPMS-CNT 10/15/2015 1
CONTENT Why we need thin passive devices? Integration options for passives Discrete thin-film capacitor platform technology High-k dielectrics Area gain by 3D integration Electrical results 10/15/2015 2
The World of IoT 10/15/2015 3
The World of IoT On average, each cow generates about 200 megabytes of information each year 10/15/2015 4
Miniaturized Application examples GPS Module Source: ESP8266 WIFI Module Ant-size radio Source: CSIRO / Engadget Implantable pressure sensors Source: 4D Systems Miniaturized chip for hearing aids Source: Stanford Univ. Source: Sensors 2014, 14, 20620-20644 Source: Fraunhofer IZM 10/15/2015 5
IoT is an evolution Source: SRI Consulting Business Intelligence/National Intelligence Council 10/15/2015 6
Miniaturization of Integrated Systems Example: WIFI modem? (EPCOS AG) (EPCOS AG) (EPCOS AG) Main Enablers More functions on chip Scaling of semiconductors New packaging technologies Integration of Passive components ( L, C, R ) 10/15/2015 7
Integrated Capacitors Applications & maximum available Si-based capacitors on chip or in package Capacitance density RF filtering matching & Analog filtering Bypassing, decoupling Charge-pumping & storage 10µF/mm² 1µF/mm² To support wide capacitance range GPUs, CPUS, DC/DC converters Sensors, Medical 100nF/mm² 10nF/mm² 1nF/mm² RF transceivers Audio filters Microcontroller Baseband ICs Si-Interposer ASICs 100pF/mm² power amplifiers Source: Fraunhofer IPMS-CNT / Yole development 10/15/2015 8
Capacitance Tuning How to address wide capacitance range? 2D 3D Dielectric Bottom Electrode 1. Dielectric constant Conventional: SiO 2 (k=3.9) HfSiON (k=7) Ta 2 O 5 (k=26) TiO 2 (k=80), STO (>100) C 0k 10/15/2015 9 A d 3. Thickness tuning Operating conditions Reliability! 2. Surface Area 3D integration Structures with high Aspect ratio
System integration options for capacitors Integrated Discrete System on Chip (SoC) Chip-on-Board Low Power Chip Capacitor Chip Substrate / Lead Frame System in Package (SiP) Thin substrates <100µm required in order to meet dense packaging requirements Interposer Integration Embedding in PCB [1] Customized solution No ext. discrete components Specialized for one technology Standardized outline (SMD package - EIA standard) Addressing multiple integration options, low costs Consumes more space compared to SoC 10/15/2015 10 [1] Source: M. Brizoux et al, Proceedings of Smart Systems Integration 2009
Platform Technology Concept Integrated Discrete System on Chip (SoC) Chip-on-Board Low Power Chip Capacitor Chip Substrate / Lead Frame System in Package (SiP) Interposer Integration Embedding in PCB [1] Customized solution No ext. discrete components Specialized for one technology Standardized outline (SMD package - EIA standard) Addressing multiple integration options, low costs Consumes more space compared to SoC 10/15/2015 11 [1] Source: M. Brizoux et al, Proceedings of Smart Systems Integration 2009
Front-End processing <100µm Platform Technology Concept Standardized Capacitor Module 1. Raw Silicon Wafer 2. Etch deep holes 3. Electrodes & dielectric 4. Electrode Patterning Standard Silicon Processing Technology Back-End processing Metallization & Contacts Grinding Dicing TF-SMD capacitor Interposer 10/15/2015 12
<100µm Platform Technology Concept Standardized Capacitor Module 3D solution Laser (stealth) dicing Conventional Blade Laser Source: Photonics.com/ Hamamatsu Planar solution No edge loss Low damage No chipping & µ-cracks TF-SMD capacitor Interposer 10/15/2015 13
TSV Capacitor component Standard SMD outline 0201 0402 10/15/2015 14
TSV Capacitor component Top Contact (Cu) Standard SMD outline Bottom Contact (Cu) 0201 0402 10/15/2015 15
TSV Capacitor component Top Contact (Cu) Bottom Contact (Cu) Single-sided contacts Double-sided contacts 10/15/2015 16
TSV Capacitor component Top Contact (Cu) Chip labeling for ease of handling Bottom Contact (Cu) 10x10 0 pf = 10pF 47pF 100pF 10/15/2015 17
Capacitor component Example of achievable capacitances Component / Technology Value Range Voltage Thickness 0201 0402 0603 1206 4.7 pf 5V 100µm planar planar planar planar 10 pf 5V 100µm planar planar planar planar 47 pf 5V 100µm planar planar planar planar 100 pf 5V 100µm planar planar planar planar 470 pf 5V 100µm planar planar planar planar 1 nf 5V 100µm planar planar planar planar 2.2 nf 5V 100µm 3D planar planar planar 4.7 nf 5V 100µm 3D 3D planar planar 10 nf 5V 100µm 3D 3D 3D planar 22 nf 5V 100µm 3D 3D planar 47 nf 5V 100µm 3D 3D 100 nf 5V 100µm 3D 3D 470 nf 5V 100µm 3D 1 µf 4V 100µm 3D 20 µf 4V 100µm 3D / interposer 0201 0402 Customizable: Other values, voltages & dimensions on request 10/15/2015 18
DEVELOPMENT & PILOT FABRICATION Capacitor Front-End processing ENVIRONMENT Capacitor Back-End processing 300 mm IPMS-CNT cleanroom 800 m² clean room, class 1000 & 650 m² laboratory area 40 Tools for Wafer Processing, Patterning, Metrology & Analytics Qualification of processes & materials on 300 mm industrial standard equipment Wafer level packaging & CSP 3D IC and heterogeneous integration Silicon & glass interposer Thin wafer processing & handling 3D stacking, hermetical sealing 10/15/2015 19
(a.u.) Time to breakdown Planar Capacitors high-k materials C 0k A d Top Electrode High-k Material stack by ALD Bottom Elektrode ALD atomic layer deposition Increased Capacitance density Lower Breakdown Voltage Steeper Field acceleration Trade-off between capacitance density and reliability thickness scaling Source: J. McPherson, IEDM2002 10/15/2015 20
Planar Capacitors Electrical results 5 4 I leak I leak (na/µf) 3 2 1 0-6 -4-2 0 2 4 6 Bias (V) 10/15/2015 21
Planar Capacitors Electrical results I leak (na/µf) 5 4 3 2 1 I leak dc/c 0 <2.5% 0-6 -4-2 0 2 4 6 Bias (V) 4 3 2 1 0-1 dc/c 0 (%) I leak (A/cm²) 1E-07 1E-08 1E-09 1E-10 I leak @ 2.5V I leak @ 5V dc/c 25 C +/- 3% 15.0 12.5 10.0 7.5 5.0 2.5 0.0-2.5 1E-11-5.0-60 -40-20 0 20 40 60 80 100 120 140 Temperature ( C) dc/c 25 C (%) Comparison: Typ. Ceramic MLCC Capacitor (X7R) Temperature: +/- 10% tolerance DC Voltage: up to 50% drop 10/15/2015 22
Going for 3D Area gain by hole integration C 0k A d Small-size holes with high aspect-ratio Allowing ultra-thin substrates Conformal deposition Of dielectric requires Enabled by ALD 10/15/2015 23
3D Capacitors Density optimization Type A Type C Type B C (nf/mm 2 ) D=120nm D=130nm D=140nm D=150nm D=160nm D=170nm P=220nm P=240nm CD and Pitch optimization for further capacitance density enhancement 250 225 200 175 150 125 100 75 50 25 0 Capacitance Leakage Pitch P= 230nm Pattern collapse D = 150nm P=260nm 60 55 50 45 40 35 30 25 20 15 10 I leak (na/µf) 10/15/2015 24
2mm 3D Capacitors Test on large area demonstrator J (A/µF) 1E-6 AR 13:1 AR 15:1 AR 20:1 1E-7 4mm² Demo AR20:1 1E-8 2mm 1E-9 1E-10 No impact of aspect ratio scaling on electrical performance Large area demonstrator shows good matching to results on test structures -4-3 -2-1 0 1 2 3 4 Bias (V) 10/15/2015 25
Reliability time to dielectric breakdown 1E-5 Stress test @ accelerated conditions J[A/cm²] 1E-6 Time to Failure (s) Good agreement between planar 10-1 and 3D capacitor reliability 1.0 1.5 2.0 2.5 3.0 3.5 10 9 10 7 10 5 10 3 10 1 1E-7 Planar 3D-Capacitor 1 10 100 t [s] Electric Field (MV/cm) 10 years 10/15/2015 26
<100µm SUMMARY TF-SMD capacitor Interposer IoT evolution is driving system miniaturization small components Addressing various integration options SoC high density capacitors in BEOL Discrete: embedding in substrates and interposer Wide capacitance bandwith due to high-k materials and area gain Ultra-thin substrates due to small holes with high aspect ratio 10/15/2015 27
MANY THANKS FOR YOUR ATTENTION contact: konrad.seidel@ipms.fraunhofer.de Special thanks to the project teams of: Visit our booth 2092 This work was supported by the Fraunhofer internal MAVO program SmartTicket 10/15/2015 28