LY68L M Bits Serial Pseudo-SRAM with SPI and QPI

Similar documents
AS6C K X 8 BIT LOW POWER CMOS SRAM

AS6C6264 8K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY. Feb

8K X 8 BIT LOW POWER CMOS SRAM

Rev. No. History Issue Date Remark

LY61L102416A 1024K X 16 BIT HIGH SPEED CMOS SRAM

AT29C K (32K x 8) 5-volt Only CMOS Flash Memory. Features. Description. Pin Configurations

AT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations

IS62/65WVS5128GALL IS62/65WVS5128GBLL. 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION

LP621024E-I Series 128K X 8 BIT CMOS SRAM. Document Title 128K X 8 BIT CMOS SRAM. Revision History. AMIC Technology, Corp.

IS62/65WVS1288GALL IS62/65WVS1288GBLL. 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION MAY 2018

AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)

IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION

LY62W K X 16 BIT LOW POWER CMOS SRAM

512K bitstwo-wire Serial EEPROM

LY62L205016A 32M Bits ( 2Mx16 / 4Mx8 Switchable) LOW POWER CMOS SRAM

ISSI IS25C02 IS25C04 2K-BIT/4K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM FEATURES DESCRIPTION. Advanced Information January 2005

LY62L102516A 1024K x 16 BIT LOW POWER CMOS SRAM

2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT29C020. Features. Description. Pin Configurations

AS7C34098A-8TIN 256K X 16 BIT HIGH SPEED CMOS SRAM

ISSI Preliminary Information January 2006

A23W8308. Document Title 262,144 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark

LY62L K X 16 BIT LOW POWER CMOS SRAM

25AA160A/B, 25LC160A/B

AS6C TINL 16M Bits LOW POWER CMOS SRAM

A24C08. AiT Semiconductor Inc. ORDERING INFORMATION

CMOS Static RAM 1 Meg (128K x 8-Bit) Revolutionary Pinout

256K x 16 4Mb Asynchronous SRAM

A24C02. AiT Semiconductor Inc. ORDERING INFORMATION

LY62L409716A 4M X 16 BIT LOW POWER CMOS SRAM

Rev. No. History Issue Date Remark

LP62S16256G-I Series. Document Title 256K X 16 BIT LOW VOLTAGE CMOS SRAM. Revision History. Rev. No. History Issue Date Remark

128Kx8 CMOS MONOLITHIC EEPROM SMD

512KX8 CMOS S-RAM (Monolithic)

A24C64. AiT Semiconductor Inc. ORDERING INFORMATION

IDT71016S/NS. CMOS Static RAM 1 Meg (64K x 16-Bit)

16Mbit, 512KX32 CMOS S-RAM MODULE

LY62L K X 16 BIT LOW POWER CMOS SRAM

AT28C K (32K x 8) Paged CMOS E 2 PROM. Features. Description. Pin Configurations

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9

4Mbit, 512KX8 5V Flash Memory (Monolithic)

MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET

64K x 16 1Mb Asynchronous SRAM

16Mbit, 512KX32 CMOS S-RAM MODULE

CMOS SRAM. K6T4008C1B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.

24AA01/24LC01B. 1K I 2 C Serial EEPROM. Description: Device Selection Table. Features: Package Types. Block Diagram. Part Number.

3.3 Volt CMOS Bus Interface 8-Bit Latches

4Mb Async. FAST SRAM Specification

CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

512K x 8 4Mb Asynchronous SRAM

IDT71V124SA/HSA. 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout

FEATURES. Single Power Supply Operation - Low voltage range: 2.70 V V

Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

Product Specification

D0 - D8 INPUT REGISTER. RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 OUTPUT REGISTER RESET LOGIC RCLK REN1

Am27C512. Advanced Micro Devices. 512 Kilobit (65,536 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

64Mbit, 2MX32 3V Flash Memory Module

512Kx32 Synchronous Pipeline Burst SRAM

ISSI IS23SC4418 IS23SC KBYTE EEPROM WITH WRITE PROTECT FUNCTION AND PROGRAMMABLE SECURITY CODE (PSC) IS23SC4418 IS23SC4428 FEATURES DESCRIPTION

Am27C020. Advanced Micro Devices. 2 Megabit (262,144 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL

CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9

My-MS. MM27C ,072 x 8 CMOS EPROM PRELIMINARY INFORMATION ISSI IS27C010 FEATURES DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

HT24LC02A CMOS 2K 2-Wire Serial EEPROM

CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16

25AA040/25LC040/25C040

MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION

4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE. Rev. No. History Issue Date Remark

WINTEC I. DESCRIPTION: III. TIMING

16Mb(1M x 16 bit) Low Power SRAM

IS42VS83200J / IS42VS16160J / IS42VS32800J

24AA128/24LC128/24FC128

24AA16/24LC16B. 16K I 2 C Serial EEPROM. Device Selection Table. Description: Features: Package Types. Block Diagram. Temp. Ranges.

A67L1618/A67L0636 Series

1M-BIT, 2M-BIT, 4M-BIT AND 8M-BIT SERIAL FLASH MEMORY WITH 4KB SECTORS AND DUAL OUTPUT SPI

93C76/86. 8K/16K 5.0V Microwire Serial EEPROM FEATURES DESCRIPTION PACKAGE TYPES BLOCK DIAGRAM

M8M644S3V9 M16M648S3V9. 8M, 16M x 64 SODIMM

3.3V CMOS Static RAM for Automotive Applications 4 Meg (256K x 16-Bit)

White Electronic Designs

ZD24C32A. I 2 C-Compatible (2-wire) Serial EEPROM. 32-Kbit (4,096 x 8) DATASHEET. Features. Description. Low Voltage Operation

4Mb Async. FAST SRAM A-die Specification

Am27C Megabit (131,072 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM

SED1180F CMOS LCD 64-COMMON DRIVERS LCD CONTR 256SEG 64 COM DUTY: 1/64

RW CH Segment Driver

256Kx72 Synchronous Pipeline SRAM

MB85R M Bit (128 K 8) Memory FRAM CMOS DS E DESCRIPTIONS FEATURES FUJITSU SEMICONDUCTOR DATA SHEET

MOS INTEGRATED CIRCUIT

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUADRUPLE BUS SWITCH WITH INDIVIDUAL ACTIVE LOW ENABLES

FEBRUARY/2008, V 1.c Alliance Memory Inc. Page 1 of 13

P8M644YA9, 16M648YA9. PIN ASSIGNMENT (Front View) 168-PIN DIMM. 4-8Mx16 SDRAM TSOP P8M644YA9 8-8Mx16 SDRAM TSOP P16M648YA9

QUICKSWITCH PRODUCTS 2.5V / 3.3V 8:1 MUX / DEMUX HIGH BANDWIDTH BUS SWITCH

P2M648YL, P4M6416YL. PIN ASSIGNMENT (Front View) 168-PIN DIMM. 8-2Mx8 SDRAM TSOP P2M648YL-XX 16-2Mx8 SDRAM TSOP P4M6416YL-XX

24AA64/24LC64/24FC64. 64K I 2 C Serial EEPROM. Device Selection Table. Description: Features: Package Types. Block Diagram. Max.

M464S0424FTS SDRAM SODIMM 4Mx64 SDRAM SODIMM based on 4Mx16, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD DQ21 DQ22 DQ23 DQ53 DQ54 DQ55 A7 BA0

D0-D17 INPUT REGISTER WRITE CONTROL LOGIC. RAM ARRAY 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 Q0-Q17

IS62WV12816DALL/DBLL IS65WV12816DALL/DBLL

QUICKSWITCH PRODUCTS HIGH-SPEED CMOS 10-BIT BUS SWITCH WITH FLOW-THROUGH PINOUT

QUICKSWITCH PRODUCTS 2.5V/3.3V 20-BIT HIGH BANDWIDTH BUS SWITCH

CMOS SyncFIFO TM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 INPUT REGISTER WRITE CONTROL LOGIC

SRAM Card with Two Rechargeable Batteries

MOS INTEGRATED CIRCUIT

QUICKSWITCH PRODUCTS 2.5V / 3.3V 20-BIT DUAL PORT, HIGH BANDWIDTH BUS SWITCH

Transcription:

REVISION HISTORY Revision Description Issue Date Rev. 0.1 Initial Issued May.6. 2016 Rev. 0.2 Revised typos May.19. 2016 Revised the address bit length from 32 bits to 24 bits Oct.13. 2016 0

FEATURES GENERAL DESCRIPTION SPI compatible bus interface - Clock rate: 33MHz(max) for normal read 100MHz(max) for fast read - Mode: SPI/QPI Low power consumption: Operating current: 30mA(MAX./SPI@33MHz) 60mA(MAX./QPI@100MHz) Single 3.3V power supply Unlimited read/write cycle Fast write time as minimum cycle time 8M x 8-bit organization -1K byte per page High Reliability Green package available Package : 8-pin 150 mil SOP The is a 64M-bit serial pseudo SRAM device organized as 8Mx8 bits. It is fabricated using very high performance, high reliability CMOS technology. The is accessed via a simple Serial Peripheral Interface(SPI) compatible serial bus. Additionally, Quad Peripheral Interface(QPI) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. The operates from a single power supply of 3.3V and can offer high data bandwidth at 100MHz clock rate and Serial Quad interface. The offers 8-lead SOP package. PIN CONFIGURATION PIN DESCRIPTION SYMBOL SPI MODE SQI MODE SI/SIOI[0] Serial Input Serial I/O[0] SO/SIO[1] Serial Output Serial I/O[1] SIO[2] - Serial I/O[2] SIO[3] - Serial I/O[3] CE# Chip Select Input SCLK Clock Signal Input VCC VSS Power Supply Ground ABSOLUTE MAXIMUN RATINGS* PARAMETER SYMBOL RATING UNIT Voltage on VCC relative to VSS VT1-0.5 to 4.6 V Voltage on any other pin relative to VSS VT2-0.5 to VCC+0.5 V Operating Temperature TA -25 to 85 Storage Temperature TSTG -65 to 150 *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. 1

POWER-UP INITIALIZATION The includes an on-chip voltage sensor used to start the self-initialization process. When VCC reaches a stable level at or above minimum VCC, the device will require 150µs to complete its self-initialization process. From the beginning of power ramp to the end of the 150µs period, SCLK should remain LOW, CE# should remain HIGH(track VCC within 200mV) and SI/SO/SIO[3:0] should remain LOW. After the 150µs period, the device requires at least one clock during CE# high to properly reset the device, and then the device is ready for normal opearion. Command/Address Latching Truth Table SPI Mode QPI Mode Command Code Cmd Addr Wait Max Wait Max DIO Cmd Addr DIO Cycle Freq. Cycle Freq. Read 03h S S 0 S 33 N/A Fast Read 0Bh S S 8 S 100 N/A Quad Read EBh S Q 6 Q 100 Q Q 6 Q 100 Write 02h S S 0 S 100 Q Q 0 Q 100 Quad Write 38h S Q 0 Q 100 Q Q 0 Q 100 Enter QPI Mode 35h S - - - 100 N/A Exit QPI Mode F5h Note: S = Serial IO, Q = Quad IO N/A Q - - - 100 2

DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. *1 MAX. UNIT Supply Voltage VCC - 3.3 - V Input High Voltage VIH Vcc-0.4 - VCC+0.2 V Input Low Voltage VIL - 0.2-0.4 V Input Leakage Current ILI VCC VIN VSS - 1-1 µa Output Leakage VCC VOUT VSS, ILO Current Output Disabled - 1-1 µa Output High Voltage VOH IOH = -0.2mA 0.8*Vcc - - V Output Low Voltage VOL IOL = +0.2mA - - 0.2*Vcc V Average Operating Power Supply Current Standby Power Supply Current ICC1 ISB1 Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25 CE# 0.2, Others at 0.2V SPI@33MHz - - 30 ma or Vcc-0.2V II/O = 0mA;f=max QPI@100MHz - - 60 ma CE# VCC - 0.2V, Others at 0.2V or VCC - 0.2V - - 300 µa 3

CAPACITANCE (TA = 25, f = 1.0MHz) PARAMETER SYMBOL MIN. MAX UNIT Input Capacitance CIN - 6 pf Input/Output Capacitance CI/O - 8 pf Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to Vcc-0.2V 1.5ns VCC/2 CL = 30pF + 1TTL, IOH/IOL = -0.2mA/+0.2mA AC ELECTRICAL CHARACTERISTICS Clock Cycle Time PARAMETER SYM. MIN. MAX. UNIT tclk@33mhz 30 - ns tclk@100mhz 10 - ns Clock low width tcl 0.45 0.55 tclk Clock high width tch 0.45 0.55 tclk Clock rise time tr - 1.5 ns Clock fall time tf - 1.5 ns CE# setup time to CLK rising edge tcsp 2.5 - ns Setup time to active CLK edge ts 2.5 - ns Hold time from active CLK edge th 2 - ns Chip disable to DQ output high-z thz - 7 ns CLK falling to output valid taclk - 7 ns Output Hold from Clock falling toh 1.5 - ns CE# low pulse width tcem - 5 us 4

SPI MODE OPERATIONS The device powers up into SPI mode by default, but can also be switched into QPI mode. 1. SPI Mode : Read Operations For all reads, data will be available taclk after the falling edge of CLK. SPI Reads can be done in three ways: 1.1. 03h : Serial CMD, Serial IO, slow frequency 1.2. 0Bh : Serial CMD, Serial IO, fast frequency 1.3 EBh : Serial CMD, Quad IO, fast frequency 1.1 SPI Read(03h) 1.2 SPI Fast Read(0Bh) 5

1.3 SPI Quad Read(EBh) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CE# taclk SI/SIO[0] 1 1 1 0 1 0 1 1 20 16 12 8 4 0 4 0 4 0 SO/SIO[1] 21 17 13 9 5 1 5 1 5 1 SIO[2] 22 18 14 10 6 2 6 2 6 2 SIO[3] 23 19 15 11 7 3 7 3 7 3 SPI Quad Read CMD(EBh) 24 Bits Address Wait Cycles Data Out1 Data Out2 Don't Care Undefined 2. SPI Mode : Write Operations SPI Writes can be done in two ways: 2.1 02h : Serial CMD, Serial IO, slow frequency 2.1 38h : Serial CMD, Quad IO, fast frequency 2.1 SPI Write(02h) 6

2.2 SPI Quad Write(38h) QPI MODE OPERATIONS 3. QPI Mode : Read Operations (EBh) 4. QPI Mode : Write Operations(38h or 02h) 7

5. QPI Mode : Enable Operation(35h) 6. QPI Mode : Quit Operation(F5h) CLK 0 1 2 CE# SIO[3:0] F 5 QPI Mode Exit CMD(F5h) Don't Care 8

PACKAGE OUTLINE DIMENSION 8-pin 150mil SOP Package Outline Dimension 9

ORDERING INFORMATION Package Type Maximum Clock Rate(MHz) Temperature Range( ) Packing Type Lyontek Item No. 8-Pin 150mil SOP 100-25 ~85 Tube Tape Reel SL SLT 10

THIS PAGE IS LEFT BLANK INTENTIONALLY. 11