Array-Structured Memory Architecture Memory Design I Professor hris H. Kim University of Minnesota Dept. of EE chriskim@ece.umn.edu 2 Semiconductor Memory lassification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Read-Write Memories (RWM) Basic storage elements of semiconductor memory RAM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM DRAM SRAM DRAM FIFO LIFO Shift Register AM FLASH SRAM: cell has gain, 6T, FAST, LOW POWER, logic compatible, differential DRAM: cell has no gain, T, refresh, slow, DRAM process, single ended, DENSE 3 4 Memory Scaling Trend Memory Scaling Trend Itoh, IBM R&D, 23 High density is the primary design goal for memories Low voltage operation is essential for low power Long retention time low Ioff High Vt is required Fast access time high Ion High Vgs-Vt is required Vdd cannot be scaled down aggressively for low power consumption Itoh, IBM R&D, 23 5 6
Why SRAMs are Important ache ore Logic ache ore Logic ache ore Logic.8μm.3μm.9μm Memories have better power efficiency compared to logic ~9.9B out of B transistors will be used for SRAMs ompany with better SRAM design will dominate σ V t Why SRAMs are Important = Area Taur, Ning Normalized I ON.4.2..8 NMOS PMOS 2X.6 X 5nm,.4.. Normalized I OFF Area is the number one concern minimum sized devices Smaller devices have larger variation Delay variation, stability, leakage is a problem entral limit theorem doesn t hold (σ/μ) 7 8 Positive Feedback: Bi-Stability Meta-Stability V i V o =V i2 V o2 V o V o V i2 V i 2 5Vo V o2 =V i V i2 = V o A V i2 = V o A V i V o2 V i2 =V o V V i 25 o A B δ B B V i = V o2 δ V i = V o2 Gain should be larger than in the transition region V i =V o2 9 SRAM Memory ell SRAM Read Operation B NMOS access transistors Read and write uses the same port: need sufficient margins One wordline to access cell Two bit lines (, B) to carry the data Almost minimum size transistors for small cell area B Both bit lines are precharged to Vdd Wordline is fired for one of the cells on bit line ell pulls down either or B Sense amp regenerates the differential signal Data should not flip after read access Driver TR must be stronger than access TR 2 2
SRAM Read Operation SRAM Read Operation bitline delay = bitline ΔV I cell bitline B 5mV Murmann class notes For high density, large number of cells share bitline and wordline Subarray organization for 32Kb: 28 s, 256 s SA out bitline is large due to large number of cells attached I cell is small due to high density cells V bitline has to be minimized for high speed < mv bitline voltage difference generated by SRAM cell Let the sense amplifier finish the job Increased noise sensitivity, circuit complexity 3 4 SRAM Read Operation: Precharge SRAM Read Operation: Precharge Option (a) Similar to dynamic logic precharge Balance transistor to equalize bitline voltages Short wordline pulse required to limit bitline swing Option (b) Pseudo-NMOS type circuit Bitline voltage clamped during read Option (c) NMOS pullup instead of PMOS Precharge levels are limited to -V t an t operate at low 5 6 SRAM ell Read Margin Vx When cell is not accessed (=) Data is safely kept inside the cell High noise margin When cell is accessed (= ) Access transistor acts as a noise source Data is pulled up to V x ell data can flip if V x rises above V tn Static Noise Margin V Q V QB Destructive read problem The size of the largest square enclosed in the butterfly curves = read static noise margin V(QB) V(QB).8.6.4.2.8.6.4.2 Good SNM.2.4.6.8 V(Q) E. Seevinck, 987, JSS Bad SNM.2.4.6.8 V(Q) 7 8 3
MOS SRAM Analysis (Read) Techniques to Improve Read Margin M 4 Q = Q = M 6 M 5 ell beta ratio = (W/L) drv / (W/L) access M bit bit J. Rabaey Increasing the size of the driver NMOS improves read margin But remember, area is the number one constraint in memory design Increasing cell size a not a good trade off 9 2 Techniques to Improve Read Margin Techniques to Improve Read Margin High V t transistors Internal node on low side needs to rise to V t or more Virtually never happens when V t is larger than half ell is extremely stable at ultra-low power design point Beta ratio constraint is relaxed smaller driver and larger access TR can be used for faster read and write SNM low V t SNM high V t Boosted cell supply Supply voltage of SRAM cell is higher than outside Makes driver stronger than access, suppressing the rise in the low side Effectively improves the beta ratio Driver NMOS can be downsized, decreasing cell size + 2 22 SRAM Write Operation B MOS SRAM Analysis (Write) M 4 Q = M 6 M 5 Q = M = = PR= ( W / L) 4 ( W / L) 6 Launch the write data on and B Word line signal is fired Low bit line value flips cell data Access TR must be stronger than PMOS load 23 24 4
SRAM ell Write Margin J. Rabaey Techniques to Improve Write Margin Sizing: access TR vs. PMOS in latch Higher voltage for access TR Virtual VDD Higher voltage = (W/L) pmos / (W/L) access Sizing Access transistor must be stronger than PMOS to pull the below the trip point (typical pull-up ratio ~.5) To avoid cell size increase, correct pull-up ratio achieved by controlling V tn and V tp 25 26 6T-SRAM Layout Until 9nm 6T-SRAM Layout From 65nm B GND ompact cell Bitlines: M2 Wordline: strapped in M3 27 28 6T SRAM ell Supply current is limited to the leakage current of transistors in the stable state 4T SRAM ell High degree of compactness High power consumption 6T versus 4T SRAM RAM Variations Many variations to the basic 6T SRAM cell More functionality, smaller cells Dual read or single write cell True multi-ported cell ontent addressable memory (AM) 4T memory cell 3T memory cell 2T memory cell T DRAM cell 29 3 5
Dual Read or Single Write ell Multi Ported ell B Two wordlines, one for each access transistor Small increase in cell size an either read two different cells in one cycle or write to one cell B B Each port has separate address Memory access bandwidth is twice (ideally) Write through : data written can be read by another port in the very same cycle 3 32 ontent Addressable Memory (AM) Smaller RAM ells Some application need to find out if anything in the memory matches a certain key value (e.g. tag) Special memory with XOR gate that compares cell value with the data on the bilines Precharged match line shared across word will stay high only when the entire word matches Needs a encoder that will output the matching address Internal nodes don t goto Need 2 wordlines, read Vdd and write ell won t work at low Vdd an have or 2 bitlines High value stored is (Read/Write) degraded Not very small, since it has Effective strength of NMOS more wires driver is reduced Refresh needed 33 34 M -T DRAM ell S X GND Write Read 2 V T /2 V sensing DD /2 Write: S is charged or discharged by asserting and. Read: harge redistribution takes places between bit line and storage capacitance DRAM ell Observations T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the T DRAM cell is destructive; read and refresh operations are necessary for correct operation. When writing a into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than S ΔV = V V PRE = V BIT V PRE ------------ S + Voltage swing is small; typically around 25 mv. 35 36 6
Sense Amp Operation -T DRAM ell apacitor V V() Metal word line M word line V PRE DV() Sense amp activated Word line activated V() t Poly n + n + Inversion layer Poly induced by plate bias ross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Uses Polysilicon-Diffusion apacitance Expensive in Area Polysilicon plate 37 38 ell Plate Si apacitor Insulator Storage Node Poly 2nd Field Oxide Advanced -T DRAM ells Refilling Poly Si Substrate Word line Insulating Layer Transfer gate ell plate Storage electrode apacitor dielectric layer Isolation Good References on RAM K. Itoh, VLSI Memory hip Design, Springer-Verlag New York, LL Y. Nakagome, M. Horiguchi, T. Kawahara, and K. Itoh, Review and future prospects of low-voltage RAM circuits, Vol. 47, No. 5/6, 23, IBM J R&D R. W. Mann, W. W. Abadeer, M. J. Breitwisch, O. Bula, et al, Ultralow-power SRAM technology, Vol. 47, No. 5/6, 23, IBM J R&D Trench ell Stacked-capacitor ell 39 4 7