PowerPC 405EP Embedded Processor Data Sheet

Features IBM PowerPC 405 32-bit RISC processor core operating up to 266MHz with 16KB D- and I- caches PC-133 synchronous DRAM (SDRAM) interface - 32-bit interface for non-ecc applications 4KB on-chip memory (OCM) External peripheral bus - Flash ROM/Boot ROM interface - Direct support for 8- or 16-bit SRAM and external peripherals - Up to five devices DMA support for memory and UARTs. - Scatter-gather chaining supported - Four channels PCI Revision 2.2 compliant interface (32-bit, up to 66MHz) - Asynchronous PCI Bus interface - Internal or external PCI Bus Arbiter Two Ethernet 10/100Mbps (full-duplex) ports with media independent interface (MII) Programmable interrupt controller supports seven external and 19 internal edge triggered or level-sensitive interrupts Programmable timers Software accessible event counters Two serial ports (16750 compatible UART) One IIC interface General purpose I/O (GPIO) available Supports JTAG for board level testing Internal processor local Bus (PLB) runs at SDRAM interface frequency Supports PowerPC processor boot from PCI memory Description Designed specifically to address embedded applications, the PowerPC 405EP (PPC405EP) provides a high-performance, low-power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation requirements. This chip contains a high-performance RISC processor core, SDRAM controller, PCI bus interface, Ethernet interface, control for external ROM and peripherals, DMA with scatter-gather support, serial ports, IIC interface, and general purpose I/O. Technology: IBM CMOS SA-27E, 0.18 µm (0.11 µm L eff ) Package: 31mm, 385-ball, enhanced plastic ball grid array (E-PBGA) Power (typical): 1.2W at 200MHz 3/19/03 While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. 1

Contents Ordering, PVR, and JTAG Information...................................................... 4 Address Map Support................................................................... 6 On-Chip Memory (OCM)................................................................. 8 PLB to PCI Interface.................................................................... 8 SDRAM Memory Controller.............................................................. 9 External Peripheral Bus Controller (EBC).................................................... 9 DMA Controller....................................................................... 10 Serial Interface....................................................................... 10 IIC Bus Interface...................................................................... 10 General Purpose IO (GPIO) Controller..................................................... 11 Universal Interrupt Controller (UIC)....................................................... 11 10/100 Mbps Ethernet MAC............................................................. 11 JTAG............................................................................... 11 Signal List........................................................................... 31 Spread Spectrum Clocking.............................................................. 44 Initialization.......................................................................... 50 Tables System Memory Address Map............................................................ 6 DCR Address Map..................................................................... 7 Signals Listed Alphabetically............................................................ 13 Signals Listed by Ball Assignment........................................................ 25 Pin Summary........................................................................ 31 Signal Functional Description............................................................ 33 Absolute Maximum Ratings............................................................. 39 Package Thermal Specifications.......................................................... 39 Recommended DC Operating Conditions................................................... 40 Input Capacitance..................................................................... 41 DC Electrical Characteristics............................................................ 42 Clocking Specifications................................................................. 43 Peripheral Interface Clock Timings........................................................ 45 I/O Specifications Group 1............................................................. 47 I/O Specifications Group 2............................................................. 49 Strapping Pin Assignments.............................................................. 50 2 3/19/03

Figures PPC405EP Embedded Controller Functional Block Diagram.................................... 5 31mm, 385-Ball E-PBGA Package........................................................ 12 5V-Tolerant Input Current............................................................... 41 Input Setup and Hold Timing Waveform.................................................... 46 Output Delay and Float Timing Waveform.................................................. 46 3/19/03 3

Ordering, PVR, and JTAG Information This section provides the part number nomenclature. For availability, contact your local IBM sales office. Product Name Order Part Number 1 Processor Frequency The part number contains a part modifier. Included in the modifier is a revision code. This refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PowerPC 405EP Embedded Processor User s Manual for details on accessing these registers. Order Part Number Key Package Rev Level PVR Value JTAG ID PPC405EP IBM25PPC405EP-3GB133C 133MHz 31mm, 385 E-PBGA B 0x51210950 0x20267049 PPC405EP IBM25PPC405EP-3GB133CZ 133MHz 31mm, 385 E-PBGA B 0x51210950 0x20267049 PPC405EP IBM25PPC405EP-3GB200C 200MHz 31mm, 385 E-PBGA B 0x51210950 0x20267049 PPC405EP IBM25PPC405EP-3GB200CZ 200MHz 31mm, 385 E-PBGA B 0x51210950 0x20267049 PPC405EP IBM25PPC405EP-3GB266C 266MHz 31mm, 385 E-PBGA B 0x51210950 0x20267049 PPC405EP IBM25PPC405EP-3GB266CZ 266MHz 31mm, 385 E-PBGA B 0x51210950 0x20267049 Note 1: Z at the end of the Order Part Number indicates a tape and reel shipping package. Otherwise, the chips are shipped in a tray. IBM Part Number Grade 3 Reliability Package 31mm, 385 E-PBGA IBM25PPC405EP-3GB266Cx Shipping Package Blank = Tray Z = Tape and reel Operational Case Temperature Range (-40 C to +85 C) Processor Speed 266 = 266MHz 200 = 200MHz 133 = 133MHz Revision Level 4 3/19/03

PPC405EP Embedded Controller Functional Block Diagram Universal Interrupt Controller Clock Control Reset Timers MMU Power Mgmt DOCM IOCM OCM SRAM OCM Control Event Counters DCRs PPC405 Processor Core DCR Bus GPIO IIC GPT UART x2 16KB D-Cache JTAG DCU Trace ICU 16KB I-Cache Arb On-chip Peripheral Bus (OPB) DMA Controller (4-Channel) OPB Bridge MAL Ethernet x2 Arb Processor Local Bus (PLB) SDRAM Controller External Bus Controller PCI Bridge 13-bit addr 32-bit data 29-bit addr 16-bit data 66 MHz max (async) MII The PPC405EP is designed using the IBM Microelectronics Blue Logic TM methodology in which major functional blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent way to create complex ASICs using IBM CoreConnect TM Bus Architecture. 3/19/03 5

Address Map Support The PPC405EP incorporates two address maps. The first address map defines the possible use of addressable memory regions that the processor can access. The second address map defines Device Configuration Register (DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EP processor through the use of mtdcr and mfdcr instructions. System Memory Address Map 4GB System Memory General Use Boot-up PCI Function Subfunction Start Address End Address Size SDRAM, External Peripherals, and PCI Memory Note: Any of the address ranges listed at right may be use for any of the above functions. 0x00000000 0xE7FFFFFF 3712MB 0xE8010000 0xE87FFFFF 8MB 0xEC000000 0xEEBFFFFF 44MB 0xEEE00000 0xEF3FFFFF 6MB 0xEF500000 0xEF5FFFFF 1MB 0xEF900000 0xFFFFFFFF 263MB Peripheral Bus Boot 1 0xFFE00000 0xFFFFFFFF 2MB PCI Boot 2 0xFFFE0000 0xFFFFFFFF 128KB PCI I/O 0xE8000000 0xE800FFFF 64KB PCI I/O 0xE8800000 0xEBFFFFFF 56MB Configuration Registers 0xEEC00000 0xEEC00007 8B Interrupt Acknowledge and Special Cycle 0xEED00000 0xEED00003 4B Local Configuration Registers 0xEF400000 0xEF40003F 64B UART0 0xEF600300 0xEF600307 8B UART1 0xEF600400 0xEF600407 8B IIC0 0xEF600500 0xEF60051F 32B Internal Peripherals OPB Arbiter 0xEF600600 0xEF60063F 64B GPIO Controller Registers 0xEF600700 0xEF60077F 128B Ethernet 0 Controller Registers 0xEF600800 0xEF6008FF 256B Ethernet 1 Controller Registers 0xEF600900 0xEF6009FF 256B Notes: 1. When peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above. 2. If PCI boot is selected, a PLB-to-PCI mapping is automatically configured at reset to the address range listed above. 3. After the boot process, software may reassign the boot memory regions for other uses. 4. All address ranges not listed above are reserved. 6 3/19/03

DCR Address Map 4KB Device Configuration Registers Function Start Address End Address Size Total DCR Address Space 1 0x000 0x3FF 1KW (4KB) 1 By function: Reserved 0x000 0x00F 16W Memory Controller Registers 0x010 0x011 2W External Bus Controller Registers 0x012 0x013 2W Reserved 0x014 0x017 2W On-Chip Memory Controller Registers 0x018 0x01F 8W Reserved 0x020 0x07F 96W PLB Registers 0x080 0x08F 16W Reserved 0x090 0x09F 16W OPB Bridge Out Registers 0x0A0 0x0A7 8W Reserved 0x0A8 0x0AF 6W Clock, Control, and Reset 0x0B0 0x0B7 8W Power Management 0x0B8 0x0BF 8W Interrupt Controller 0x0C0 0x0CF 16W Reserved 0x0D0 0x0FF 48W DMA Controller Registers 0x100 0x13F 64W Reserved 0x140 0x17F 64W Ethernet MAL Registers 0x180 0x1FF 128W Event Counters 0x200 0x203 4W Reserved 0x204 0x3FF 508W Notes: 1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register, or 1 kiloword (KW) (which equals 4 KB). 3/19/03 7

On-Chip Memory (OCM) The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the processor core. Features include: Low-latency access to critical instructions and data Performance identical to cache hits without misses Contents change only under program control PLB to PCI Interface The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor and local memory. This interface is compliant with version 2.2 of the PCI Specification. Features include: Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is optional and can be disabled for systems which employ an external arbiter. PCI bus frequency up to 66MHz - Asynchronous operation from 1/8 PLB frequency to 66MHz maximum 32-bit PCI address/data bus Power Management: - PCI Bus Power Management v1.1 compliant Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI Buffering between PLB and PCI: - PCI target 64-byte write post buffer - PCI target 96-byte read prefetch buffer - PLB slave 32-byte write post buffer - PLB slave 64-byte read prefetch buffer Error tracking/status Supports PCI target side configuration Supports processor access to all PCI address spaces: - Single-byte PCI I/O reads and writes - PCI memory single-beat and prefetch-burst reads and single-beat writes - Single-byte PCI configuration reads and writes (type 0 and type 1) - PCI interrupt acknowledge 8 3/19/03

- PCI special cycle Supports PCI target access to all PLB address spaces Supports PowerPC processor boot from PCI memory SDRAM Memory Controller The PPC405EP Memory Controller core provides a low latency access path to SDRAM memory. A variety of system memory configurations are supported. The memory controller supports up to two physical banks. Up to 256MB per bank are supported, up to a maximum of 1GB. Memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: 11x8 to 13x11 addressing for SDRAM (2 banks) 32-bit memory interface support Programmable address compare for each bank of memory Industry standard 168-pin DIMMS are supported (some configurations) Up to 133MHz memory with PC-133 support - 266MHz and 133MHz processors support 133MHz memory - 200MHz processors support 100 MHz memory 4MB to 256MB per bank Programmable address mapping and timing Auto refresh Page mode accesses with up to 4 open pages Power management (self-refresh) External Peripheral Bus Controller (EBC) Supports five banks of ROM, EPROM, SRAM, Flash memory, or slave peripherals Up to 66MHz operation Burst and non-burst devices 8- and 16-bit byte-addressable data bus width support Latch data on Ready, synchronous or asynchronous Programmable 2K clock time-out counter with disable for Ready Programmable access timing per device - 0 255 wait states for non-bursting devices - 0 31 burst wait states for first access and up to 7 wait states for subsequent accesses 3/19/03 9

- Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (0 to 3 clock cycles) relative to CS Programmable address mapping Peripheral Device pacing with external Ready DMA Controller Supports memory-to-memory transfers Four channels Scatter/gather capability for programming multiple DMA operations 32-bit addressing Address increment or decrement Internal 32-byte data buffering capability Serial Interface One 8-pin UART and one 2-pin (Tx and Rx only) UART interface provided Internal serial clock to allows a wide range of baud rates Register compatibility with NS16750 register set Complete status reporting capability Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode Fully programmable serial-interface characteristics Supports DMA using internal DMA engine IIC Bus Interface Compliant with Phillips Semiconductors I 2 C Specification, dated 1995 Operation at 100kHz or 400kHz 8-bit data 10- or 7-bit address Slave transmitter and receiver Master transmitter and receiver Multiple bus masters Supports fixed V DD IIC interface 10 3/19/03

Two independent 4 x 1 byte data buffers Twelve memory-mapped, fully programmable configuration registers One programmable interrupt request signal Provides full management of all IIC bus protocol Programmable error recovery General Purpose IO (GPIO) Controller Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses All GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, threestated if output bit is 1) Universal Interrupt Controller (UIC) The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the various sources of interrupts and the local PowerPC processor. Features include: Supports seven external and 19 internal interrupts Edge triggered or level-sensitive Positive or negative active Non-critical or critical interrupt to processor core Programmable critical interrupt priority ordering Programmable critical interrupt vector for faster vector processing 10/100 Mbps Ethernet MAC Two ports capable of handling full/half duplex 100Mbps and 10Mbps operation Uses the medium independent interface (MII) to the physical layer (PHY not included on chip) JTAG IEEE 1149.1 test access port IBM RISCWatch debugger support JTAG Boundary Scan Description Language (BSDL) 3/19/03 11

31mm, 385-Ball E-PBGA Package Top View Gold Gate Release Corresponds to A1 Ball Location 15.5 TYP C Note: All dimensions are in mm. 0.20 C Bottom View 0.20 31.0 27.98 A 0.25 C 0.35 C 31.0±0.2 AB AC AA Y V W T U P R N M K L H J F G D E B C A Thermal Balls 1.27 TYP PCB Substrate Mold Compound B 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 0.65 ± 0.05 SOLDERBALL x 385 0.30 s C A s B s 0.15 s C 0.6±0.1 2.49 REF 2.65 max 12 3/19/03

Pin Lists The PPC405EP embedded controller is available in a 31 millimeter, 385-ball E-PBGA package. The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and the alternate signal in brackets. Multiplexed signals appear alphabetically multiple times in the list once for each signal name on the ball. The page number listed gives the page in Signal Functional Description on page 33 where the signals in the indicated interface group begin. Signals Listed Alphabetically (Part 1 of 12) Signal Name Ball Interface Group Page A AB21 AV DD AC20 BA0 Y15 BA1 AC16 BankSel0 AB13 BankSel1 AC13 System 37 SDRAM 35 SDRAM 35 CAS Y14 SDRAM 35 ClkEn0 AB14 ClkEn1 AC14 DQM0 AC10 DQM1 AA7 DQM2 W04 DQM3 U02 SDRAM 35 SDRAM 35 EMCMDClk Y06 Ethernet 34 EMCMDIO AA5 Ethernet 34 EMC0Tx0D0 U03 EMC0Tx0D1 N03 EMC0Tx0D2 L01 Ethernet 34 EMC0Tx0D3 P03 EMC0Tx0En W01 Ethernet 34 EMC0Tx0Err V03 Ethernet 34 EMC0Tx1D0 B15 EMC0Tx1D1 C14 EMC0Tx1D2 A15 Ethernet 34 EMC0Tx1D3 D14 EMC0Tx1En A16 Ethernet 34 EMC0Tx1Err C15 Ethernet 34 ExtReset A03 External Slave Peripheral 35 3/19/03 13

Signals Listed Alphabetically (Part 2 of 12) Signal Name Ball Interface Group Page A01 A02 A07 A12 A17 A22 A23 B01 B02 B22 B23 C03 C21 D04 D20 E05 E09 E12 E15 E19 G01 G23 J05 J19 K10-K14 L10-L14 Ground Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls. 38 14 3/19/03

Signals Listed Alphabetically (Part 3 of 12) Signal Name Ball Interface Group Page M01 M05 M10-M14 M19 M20 M23 N10-N14 P10-P14 R05 R19 U01 U23 W05 W09 W12 W15 Power Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal W19 balls. Y04 Y20 AA03 AA21 AB01 AB02 AB22 AB23 AC01 AC02 AC07 AC12 AC17 AC22 AC23 38 3/19/03 15

Signals Listed Alphabetically (Part 4 of 12) Signal Name Ball Interface Group Page GPIO00[PerBLast] A09 GPIO01[TS1E] AA23 GPIO02[TS2E] Y22 GPIO03[TS1O] Y23 GPIO04[TS2O] W21 GPIO05[TS3] U20 GPIO06[TS4] V23 GPIO07[TS5] U21 GPIO08[TS6] U22 GPIO09[TrcClk] T21 GPIO10[PerCS1] C02 GPIO11[PerCS2] E03 GPIO12[PerCS3] D03 GPIO13[PerCS4] D05 GPIO14[PerAddr03] B04 GPIO15[PerAddr04] A04 GPIO16[PerAddr05] A05 System 37 GPIO17[IRQ0] W22 GPIO18[IRQ1] W23 GPIO19[IRQ2] V21 GPIO20[IRQ3] V22 GPIO21[IRQ4] T22 GPIO22[IRQ5] R20 GPIO23[IRQ6] T23 GPIO24[UART0_DCD] M04 GPIO25[UART0_DSR] K01 GPIO26[UART0_RI] L04 GPIO27[UART0_DTR] J01 GPIO28[UART1_Rx] J02 GPIO29[UART1_Tx] J03 GPIO30[RejectPkt0] W20 GPIO31[RejectPkt1] Y21 Halt C22 System 37 IICSCL AB4 IICSDA Y01 [IRQ0]GPIO17 W22 [IRQ1]GPIO18 W23 [IRQ2]GPIO19 V21 [IRQ3]GPIO20 V22 [IRQ4]GPIO21 T22 [IRQ5]GPIO22 R20 [IRQ6]GPIO23 T23 Internal Peripheral 36 Interrupts 36 16 3/19/03

Signals Listed Alphabetically (Part 5 of 12) MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut1 Signal Name Ball Interface Group Page AB15 AB16 AB17 AA17 AC18 AA18 AC19 AB19 Y18 AA19 Y19 AA20 AC21 AA14 Y13 SDRAM Note: During a CAS cycle MemAddr00 is the least significant bit (lsb) on this bus. SDRAM 35 35 3/19/03 17

Signals Listed Alphabetically (Part 6 of 12) MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Signal Name Ball Interface Group Page AB12 AA12 AC11 AA11 Y11 AA10 AC9 AB9 AC8 Y09 AA8 AB7 AB6 Y07 AA6 AC5 AB5 AC4 Y05 AA4 AB3 Y03 W03 V04 W02 U04 V02 T04 T02 R04 R03 R02 B11 B09 B19 C17 D13 E06 E07 E08 SDRAM Note: MemData00 is the most significant bit (msb) on this bus. Power 38 35 18 3/19/03

Signals Listed Alphabetically (Part 7 of 12) Signal Name Ball Interface Group Page E16 E17 E18 E21 F05 F19 F23 G05 G19 H05 H19 H22 K04 K20 K23 M22 N01 P20 Power 38 P23 T05 T19 T20 U05 U19 V01 V05 V19 W06 W07 W08 W16 W17 W18 Y12 AC06 3/19/03 19

Signals Listed Alphabetically (Part 8 of 12) PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 Signal Name Ball Interface Group Page B16 C16 B17 D16 B18 D17 C18 A19 D18 C19 A20 B20 C20 C23 D21 D22 J22 J23 K21 K22 L21 L22 L23 M21 N23 N22 N21 P22 P21 R23 R22 R21 A18 PCI Note: PCIAD31 is the most significant bit (msb) on this bus. PCIC1/BE1 D19 PCIC2/BE2 L20 PCI 33 PCIC3/BE3 N20 PCIClk B21 PCI 33 PCIDevSel H21 PCI 33 PCIFrame F22 PCI 33 PCIGnt0/Req D23 PCI 33 PCIGnt1 E23 PCIGnt2 F21 PCI 33 PCIIDSel A21 PCI 33 33 20 3/19/03

Signals Listed Alphabetically (Part 9 of 12) Signal Name Ball Interface Group Page PCIINT[PerWE] D15 PCI 33 PCIIRDY H20 PCI 33 PCIParity J21 PCI 33 PCIPErr H23 PCI 33 PCIReq0/Gnt E20 PCIReq1 F20 PCI 33 PCIReq2 E22 PCIReset G20 PCI 33 PCISErr J20 PCI 33 PCIStop G22 PCI 33 PCITRDY G21 PCI 33 [PerAddr03]GPIO14 B04 [PerAddr04]GPIO15 A04 [PerAddr05]GPIO16 A05 PerAddr06 D07 PerAddr07 B06 PerAddr08 A06 PerAddr09 D08 PerAddr10 C07 PerAddr11 B07 PerAddr12 C08 PerAddr13 B08 PerAddr14 D09 PerAddr15 A08 PerAddr16 C09 PerAddr17 D10 External Slave Peripheral Note: PerAddr3 is the most significant bit (msb) on this bus. 35 PerAddr18 C10 PerAddr19 B10 PerAddr20 D11 PerAddr21 A10 PerAddr22 C11 PerAddr23 A11 PerAddr24 D12 PerAddr25 B12 PerAddr26 C12 PerAddr27 A13 PerAddr28 B13 PerAddr29 C13 PerAddr30 A14 PerAddr31 B14 [PerBLast]GPIO00 A09 External Slave Peripheral 35 PerClk C04 External Slave Peripheral 35 3/19/03 21

Signals Listed Alphabetically (Part 10 of 12) PerCS0 [PerCS1]GPIO10 [PerCS2]GPIO11 [PerCS3]GPIO12 [PerCS4]GPIO13 PerData00 E04 C02 E03 D03 D05 P02 External Slave Peripheral 35 PerData01 N04 PerData02 P01 PerData03 M02 PerData04 M03 PerData05 L02 PerData06 L03 PerData07 K02 External Slave Peripheral PerData08 K03 Note: PerData00 is the most significant bit (msb) on this bus. 35 PerData09 H01 PerData10 J04 PerData11 G02 PerData12 G04 PerData13 H04 PerData14 F01 PerData15 D01 PerOE F04 External Slave Peripheral 35 PerReady B03 External Slave Peripheral 35 PerR/W D02 External Slave Peripheral 35 PerWBE0 F03 External Slave Peripheral 35 PerWBE1 E01 [PerWE]PCIINT D15 External Slave Peripheral 35 PHY0Col0 AB8 PHY0Col1 C05 Ethernet 34 PHY0CrS0 AA9 PHY0CrS1 B05 Ethernet 34 PHY0Rx0Clk AB10 Ethernet 34 PHY0Rx0D0 Y16 PHY0Rx0D1 AA22 PHY0Rx0D2 AA16 Ethernet 34 PHY0Rx0D3 AA13 PHY0Rx0DV Y10 Ethernet 34 PHY0Rx0Err AB11 Ethernet 34 PHY0Rx1Clk E02 Ethernet 34 PHY0Rx1D0 R01 PHY0Rx1D1 PHY0Rx1D2 PHY0Rx1D3 Signal Name Ball Interface Group Page H03 G03 F02 Ethernet 34 22 3/19/03

Signals Listed Alphabetically (Part 11 of 12) Signal Name Ball Interface Group Page PHY0Rx1DV D06 Ethernet 34 PHY0Rx1Err C01 Ethernet 34 PHY0Tx0Clk Y08 PHY0Tx1Clk C06 Ethernet 34 SysClk AB18 System 37 RAS AA15 SDRAM 35 [RejectPkt0]GPIO30 W20 System 37 [RejectPkt1]GPIO31 Y21 System 37 Reserved Other 38 SysErr Y17 System 37 SysReset AB20 System 37 TCK Y02 JTAG 37 TDI AA1 JTAG 37 TDO AA2 JTAG 37 TestEn V20 System 37 TMS AC3 JTAG 37 TRST H02 JTAG 37 [TS1E]GPIO01 AA23 [TS2E]GPIO02 Y22 [TS1O]GPIO03 Y23 [TS2O]GPIO04 W21 [TS3]GPIO05 U20 Trace 38 [TS4]GPIO06 V23 [TS5]GPIO07 U21 [TS6]GPIO08 U22 [TrcClk]GPIO09 T21 Trace 38 UART0_CTS T03 [UART0_DCD]GPIO24 M04 [UART0_DSR]GPIO25 K01 [UART0_DTR]GPIO27 J01 [UART0_RI]GPIO26 L04 UART0_RTS N02 UART0_Rx T01 UART0_Tx P04 [UART1_Rx]GPIO28 J02 [UART1_Tx]GPIO29 J03 Internal Peripheral 36 Internal Peripheral 36 3/19/03 23

Signals Listed Alphabetically (Part 12 of 12) Signal Name Ball Interface Group Page V DD E10 V DD E11 V DD E13 V DD E14 V DD K05 V DD K19 V DD L05 V DD L19 V DD N05 Power 38 V DD N19 V DD P05 V DD P19 V DD W10 V DD W11 V DD W13 V DD W14 WE AC15 SDRAM 35 24 3/19/03

Signals Listed by Ball Assignment (Part 1 of 6) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name A01 B01 C01 PHY0Rx1Err D01 PerData15 A02 B02 C02 GPIO10[PerCS1] D02 PerR/W A03 ExtReset B03 PerReady C03 D03 GPIO12[PerCS3] A04 GPIO15[PerAddr04] B04 GPIO14[PerAddr03] C04 PerClk D04 A05 GPIO16[PerAddr05] B05 PHY0CrS1 C05 PHY0Col1 D05 GPIO13[PerCS4] A06 PerAddr08 B06 PerAddr07 C06 PHY0Tx1Clk D06 PHY0Rx1DV A07 B07 PerAddr11 C07 PerAddr10 D07 PerAddr06 A08 PerAddr15 B08 PerAddr13 C08 PerAddr12 D08 PerAddr09 A09 GPIO00[PerBLast] B09 C09 PerAddr16 D09 PerAddr14 A10 PerAddr21 B10 PerAddr19 C10 PerAddr18 D10 PerAddr17 A11 PerAddr23 B11 C11 PerAddr22 D11 PerAddr20 A12 B12 PerAddr25 C12 PerAddr26 D12 PerAddr24 A13 PerAddr27 B13 PerAddr28 C13 PerAddr29 D13 A14 PerAddr30 B14 PerAddr31 C14 EMC0Tx1D1 D14 EMC0Tx1D3 A15 EMC0Tx1D2 B15 EMC0Tx1D0 C15 EMC0Tx1Err D15 PCIINT[PerWE] A16 EMC0Tx1En B16 PCIAD00 C16 PCIAD01 D16 PCIAD03 A17 B17 PCIAD02 C17 D17 PCIAD05 A18 PCIC0/BE0 B18 PCIAD04 C18 PCIAD06 D18 PCIAD08 A19 PCIAD07 B19 C19 PCIAD09 D19 PCIC1/BE1 A20 PCIAD10 B20 PCIAD11 C20 PCIAD12 D20 A21 PCIIDSel B21 PCIClk C21 D21 PCIAD14 A22 B22 C22 Halt D22 PCIAD15 A23 B23 C23 PCIAD13 D23 PCIGnt0/Req 3/19/03 25

Signals Listed by Ball Assignment (Part 2 of 6) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name E01 PerWBE1 F01 PerData14 G01 H01 PerData09 E02 PHY0Rx1Clk F02 PHY0Rx1D3 G02 PerData11 H02 TRST E03 GPIO11[PerCS2] F03 PerWBE0 G03 PHY0Rx1D2 H03 PHY0Rx1D1 E04 PerCS0 F04 PerOE G04 PerData12 H04 PerData13 E05 F05 G05 H05 E06 F06 No ball G06 No ball H06 No ball E07 F07 No ball G07 No ball H07 No ball E08 F08 No ball G08 No ball H08 No ball E09 F09 No ball G09 No ball H09 No ball E10 V DD F10 No ball G10 No ball H10 No ball E11 V DD F11 No ball G11 No ball H11 No ball E12 F12 No ball G12 No ball H12 No ball E13 V DD F13 No ball G13 No ball H13 No ball E14 V DD F14 No ball G14 No ball H14 No ball E15 F15 No ball G15 No ball H15 No ball E16 F16 No ball G16 No ball H16 No ball E17 F17 No ball G17 No ball H17 No ball E18 F18 No ball G18 No ball H18 No ball E19 F19 G19 H19 E20 PCIReq0/Gnt F20 PCIReq1 G20 PCIReset H20 PCIIRDY E21 F21 PCIGnt2 G21 PCITRDY H21 PCIDevSel E22 PCIReq2 F22 PCIFrame G22 PCIStop H22 E23 PCIGnt1 F23 G23 H23 PCIPErr 26 3/19/03

Signals Listed by Ball Assignment (Part 3 of 6) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name J01 GPIO27[UART0_DTR] K01 GPIO25[UART0_DSR] L01 EMC0Tx0D2 M01 J02 GPIO28[UART1_Rx] K02 PerData07 L02 PerData05 M02 PerData03 J03 GPIO29[UART1_Tx] K03 PerData08 L03 PerData06 M03 PerData04 J04 PerData10 K04 L04 GPIO26[UART0_RI] M04 GPIO24[UART0_DCD] J05 K05 V DD L05 V DD M05 J06 No ball K06 No ball L06 No ball M06 No ball J07 No ball K07 No ball L07 No ball M07 No ball J08 No ball K08 No ball L08 No ball M08 No ball J09 No ball K09 No ball L09 No ball M09 No ball J10 No ball K10 L10 M10 J11 No ball K11 L11 M11 J12 No ball K12 L12 M12 J13 No ball K13 L13 M13 J14 No ball K14 L14 M14 J15 No ball K15 No ball L15 No ball M15 No ball J16 No ball K16 No ball L16 No ball M16 No ball J17 No ball K17 No ball L17 No ball M17 No ball J18 No ball K18 No ball L18 No ball M18 No ball J19 K19 V DD L19 V DD M19 J20 PCISErr K20 L20 PCIC2/BE2 M20 J21 PCIParity K21 PCIAD18 L21 PCIAD20 M21 PCIAD23 J22 PCIAD16 K22 PCIAD19 L22 PCIAD21 M22 J23 PCIAD17 K23 L23 PCIAD22 M23 3/19/03 27

Signals Listed by Ball Assignment (Part 4 of 6) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name N01 P01 PerData02 R01 PHY0Rx1D0 T01 UART0_Rx N02 UART0_RTS P02 PerData00 R02 MemData31 T02 MemData28 N03 EMC0Tx0D1 P03 EMC0Tx0D3 R03 MemData30 T03 UART0_CTS N04 PerData01 P04 UART0_Tx R04 MemData29 T04 MemData27 N05 V DD P05 V DD R05 T05 N06 No ball P06 No ball R06 No ball T06 No ball N07 No ball P07 No ball R07 No ball T07 No ball N08 No ball P08 No ball R08 No ball T08 No ball N09 No ball P09 No ball R09 No ball T09 No ball N10 P10 R10 No ball T10 No ball N11 P11 R11 No ball T11 No ball N12 P12 R12 No ball T12 No ball N13 P13 R13 No ball T13 No ball N14 P14 R14 No ball T14 No ball N15 No ball P15 No ball R15 No ball T15 No ball N16 No ball P16 No ball R16 No ball T16 No ball N17 No ball P17 No ball R17 No ball T17 No ball N18 No ball P18 No ball R18 No ball T18 No ball N19 V DD P19 V DD R19 T19 N20 PCIC3/BE3 P20 R20 GPIO22[IRQ5] T20 N21 PCIAD26 P21 PCIAD28 R21 PCIAD31 T21 GPIO09[TrcClk] N22 PCIAD25 P22 PCIAD27 R22 PCIAD30 T22 GPIO21[IRQ4] N23 PCIAD24 P23 R23 PCIAD29 T23 GPIO23[IRQ6] 28 3/19/03

Signals Listed by Ball Assignment (Part 5 of 6) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name U01 V01 W01 EMC0Tx0En Y01 IICSDA U02 DQM3 V02 MemData26 W02 MemData24 Y02 TCK U03 EMC0Tx0D0 V03 EMC0Tx0Err W03 MemData22 Y03 MemData21 U04 MemData25 V04 MemData23 W04 DQM2 Y04 U05 V05 W05 Y05 MemData18 U06 No ball V06 No ball W06 Y06 EMC0MDClk U07 No ball V07 No ball W07 Y07 MemData13 U08 No ball V08 No ball W08 Y08 PHY0Tx0Clk U09 No ball V09 No ball W09 Y09 MemData09 U10 No ball V10 No ball W10 V DD Y10 PHY0Rx0DV U11 No ball V11 No ball W11 V DD Y11 MemData04 U12 No ball V12 No ball W12 Y12 U13 No ball V13 No ball W13 V DD Y13 MemClkOut1 U14 No ball V14 No ball W14 V DD Y14 CAS U15 No ball V15 No ball W15 Y15 BA0 U16 No ball V16 No ball W16 Y16 PHY0Rx0D0 U17 No ball V17 No ball W17 Y17 SysErr U18 No ball V18 No ball W18 Y18 MemAddr08 U19 V19 W19 Y19 MemAddr10 U20 GPIO05[TS3] V20 TestEn W20 GPIO30[RejectPkt0] Y20 U21 GPIO07[TS5] V21 GPIO19[IRQ2] W21 GPIO04[TS2O] Y21 GPIO31[RejectPkt1] U22 GPIO08[TS6] V22 GPIO20[IRQ3] W22 GPIO17[IRQ0] Y22 GPIO02[TS2E] U23 V23 GPIO06[TS4] W23 GPIO18[IRQ1] Y23 GPIO03[TS1O] 3/19/03 29

Signals Listed by Ball Assignment (Part 6 of 6) Ball Signal Name Ball Signal Name Ball Signal Name Ball Signal Name AA01 TDI AB01 AC01 AA02 TDO AB02 AC02 AA03 AB03 MemData20 AC03 TMS AA04 MemData19 AB04 IICSCL AC04 MemData17 AA05 EMC0MDIO AB05 MemData16 AC05 MemData15 AA06 MemData14 AB06 MemData12 AC06 AA07 DQM1 AB07 MemData11 AC07 AA08 MemData10 AB08 PHY0Col0 AC08 MemData08 AA09 PHY0CrS0 AB09 MemData07 AC09 MemData06 AA10 MemData05 AB10 PHY0Rx0Clk AC10 DQM0 AA11 MemData03 AB11 PHY0Rx0Err AC11 MemData02 AA12 MemData01 AB12 MemData00 AC12 AA13 PHY0Rx0D3 AB13 BankSel0 AC13 BankSel1 AA14 MemClkOut0 AB14 ClkEn0 AC14 ClkEn1 AA15 RAS AB15 MemAddr00 AC15 WE AA16 PHY0Rx0D2 AB16 MemAddr01 AC16 BA1 AA17 MemAddr03 AB17 MemAddr02 AC17 AA18 MemAddr05 AB18 SysClk AC18 MemAddr04 AA19 MemAddr09 AB19 MemAddr07 AC19 MemAddr06 AA20 MemAddr11 AB20 SysReset AC20 AV DD AA21 AB21 A AC21 MemAddr12 AA22 PHY0Rx0D1 AB22 AC22 AA23 GPIO01[TS1E] AB23 AC23 30 3/19/03

Signal List The following table provides a summary of the number of package pins associated with each functional interface group. In the table Signal Functional Description on page 33, each external signal is listed along with a short description of the signal function. Active-low signals (for example, RAS) are marked with an overline. Please see Signals Listed Alphabetically on page 13 for the pin (ball) number to which each signal is assigned. Multiplexed Pins Some signals are multiplexed on the same package pin (ball) so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in Signals Listed Alphabetically on page 13. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. In addition to multiplexing, many pins are also multi-purpose. For example, in the PCI interface PCIC3:0/BE3:0 serves as both Command and Byte Enable signals. In this example, the pins are also bidirectional, serving as both inputs and outputs. Initialization Strapping One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see Initialization on page 50). Note that the use of these pins for strapping is not considered multiplexing since the strapping function is not programmable. Pull-Up and Pull-Down Resistors Pin Summary Group No. of Pins Non multiplexed 215 Multiplexed 33 Total Signal Pins 248 43 V DD 16 Gnd 53 Thermal (and Gnd) 25 Reserved 0 Total Pins 385 Pull-up and pull-down resistors are used for strapping during reset and to retain unused or undriven inputs in an appropriate state. The recommended pull-up value of 3kΩ to +3.3V (10kΩ to +5V can be used on 5V tolerant I/Os) and pull-down value of 1kΩ to, applies only to individually terminated signals. To prevent possible damage to the device, I/Os capable of becoming outputs must never be tied together and terminated through a common resistor. 3/19/03 31

If your system-level test methodology permits, input-only signals can be connected together and terminated through either a common resistor or directly to +3.3V or. When a resistor is used, its value must ensure that the grouped I/Os reach a valid logic zero or logic one state when accounting for the total input current into the PPC405EP. Unused I/Os Strapping of some pins may be necessary when they are unused. Although the PPC405EP requires only the pull-up and pull-down terminations as specified in the Signal Functional Description on page 33, good design practice is to terminate all unused inputs or to configure I/Os such that they always drive. If unused, the peripheral, SDRAM, and PCI buses should be configured and terminated as follows: Peripheral interface PerAddr03:31, PerData00:15, and all of the control signals are driven by default. Terminate PerReady high. SDRAM Program SDRAM0_CFG[EMDULR]=1 and SDRAM0_CFG[DCE]=1. This causes the PPC405EP to actively drive all of the SDRAM address, data, and control signals. PCI The PCI pull-up requirements given in the Signal Functional Description apply only when the PCI interface is being used. When the PCI bridge is unused, configure the PCI controller to park on the bus and actively drive PCIAD31:00, PCIC3:0/BE3:0, and the remaining PCI control signals by doing the following: - Strap the PPC405EP to disable the internal PCI arbiter. - Individually connect PCISErr, PCIPErr, PCITRDY, and PCIStop through 3.3kΩ resistors to +3.3V. - Terminate PCIReq1:2 to +3.3V. - Terminate PCIReq0/Gnt to. For selected interfaces, it is possible to turn off input receivers for some or all of the signals on that interface. Control for this receiver gating is in register CPC0_CR1. When this gating capability is applied to unused signals, it is not necessary to strap them. Refer to the PowerPC 405EP Embedded Processor User s Manual for details. External Bus Control Signals All peripheral bus control signals (PerCS0:4, PerR/W, PerWBE0:1, PerOE, PerWE, PerBLast) are set to the high-impedance state when ExtReset=0. In addition, as detailed in the PowerPC 405EP Embedded Processor User s Manual, the peripheral bus controller can be programmed via EBC0_CFG to float some of these control signals between transactions. As a result, a pull-up resistor should be added to those control signals where an undriven state may affect any devices receiving that particular signal. The following table lists all of the I/O signals provided by the PPC405EP. Please refer to Signals Listed Alphabetically on page 13 for the pin number to which each signal is assigned. 32 3/19/03

Signal Functional Description (Part 1 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See External Bus Control Signals on page 32. Signal Name Description I/O Type Notes PCI Interface PCIAD31:00 PCI Address/Data Bus. Multiplexed address and data bus. I/O PCIC3:0/BE3:0 PCI bus command and byte enables. I/O PCIClk PCIFrame PCIParity PCIIRDY PCITRDY PCIStop PCIDevSel PCIIDSel PCIINT PCISErr PCIPErr PCIClk is used as the asynchronous PCI clock when in asynch mode. PCIFrame is driven by the current PCI bus master to indicate the beginning and duration of a PCI access. PCI parity. Parity is even across PCIAD00:31 and PCIC3:0/BE3:0. PCIParity is valid one cycle after either an address or data phase. The PCI device that drove PCIAD00:31 is responsible for driving PCIParity on the next PCI bus clock. PCIIRDY is driven by the current PCI bus master. Assertion of PCIIRDY indicates that the PCI initiator is ready to transfer data. The target of the current PCI transaction drives PCITRDY. Assertion of PCITRDY indicates that the PCI target is ready to transfer data. The target of the current PCI transaction can assert PCIStop to indicate to the requesting PCI master that it wants to end the current transaction. PCIDevSel is driven by the target of the current PCI transaction. A PCI target asserts PCIDevSel when it has decoded an address and command encoding and claims the transaction. PCIIDSel is used during configuration cycles to select the PCI slave interface for configuration. PCI interrupt. Open-drain output (two states; 0 or open circuit) or Peripheral write enable. Low when any of the four PerWBE0:3 write byte enables are low. PCISErr is used for reporting address parity errors or catastrophic failures detected by a PCI target. PCIPErr is used for reporting data parity errors on PCI transactions. PCIPErr is driven active by the device receiving PCIAD00:31, PCIC3:0/BE3:0, and PCIParity, two PCI clocks following the data in which bad parity is detected. PCIReset PCI specific reset. O PCIReq0/Gnt Multipurpose signal, used as PCIReq0 when internal arbiter is used, and as Gnt when external arbiter is used. I I/O I/O I/O I/O I/O I/O I O I/O I/O I 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 3.3V PCI 2 2 2 2 2 2 2 3/19/03 33

Signal Functional Description (Part 2 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See External Bus Control Signals on page 32. Signal Name Description I/O Type Notes PCIReq1:2 PCIReq input when internal arbiter is used. I PCIGnt0/Req Gnt0 when internal arbiter is used or Req when external arbiter is used. PCIGnt1:2 PCIGnt output when internal arbiter is used. O Ethernet Interface PHY0Rx0:1D3:0 EMC0Tx0:1D3:0 PHY0Rx0:1Err Received data. This is a nibble wide bus from the PHY. The data is synchronous with the PHY0RxClk. Transmit data. A nibble wide data bus towards the net. The data is synchronous to the PHY0TxClk. Receive Error. This signal comes from the PHY and is synchronous to the PHY0RxClk. PHY0Rx0:1Clk Receive Medium clock. This signal is generated by the PHY. I PHY0Rx0:1DV PHY0CrS0:1 EMC0Tx0:1Err EMC0Tx0:1En PHY0Tx0:1Clk Receive Data Valid. Data on the Data Bus is valid when this signal is activated. Deassertion of this signal indicates end of the frame reception. Carrier Sense signal from the PHY. This is an asynchronous signal. Transmit Error. This signal is generated by the Ethernet controller, is connected to the PHY and is synchronous with the PHYTxClk. It informs the PHY that an error was detected. Transmit Enable. This signal is driven by the EMAC to the PHY. Data is valid during the active state of this signal. Deassertion of this signal indicates end of frame transmission. This signal is synchronous to the PHY0TxClk. This clock comes from the PHY and is the Medium Transmit clock. PHY0Col0:1 Collision signal from the PHY. This is an asynchronous signal. I EMC0MDClk EMC0MDIO Management Data Clock. The MDClk is sourced to the PHY. Management information is transferred synchronously with respect to this clock. Management Data Input/Output is a bidirectional signal between the Ethernet controller and the PHY. It is used to transfer control and status information. O I O I I I O O I O I/O 3.3V PCI 3.3V PCI 3.3V PCI 1 1 1 1 1 1 1 1 34 3/19/03

Signal Functional Description (Part 3 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See External Bus Control Signals on page 32. Signal Name Description I/O Type Notes SDRAM Interface MemData00:31 MemAddr12:00 Memory data bus. Notes: 1. MemData00 is the most significant bit (msb). 2. MemData31 is the least significant bit (lsb). Memory address bus. Notes: 1. MemAddr12 is the most significant bit (msb). 2. MemAddr00 is the least significant bit (lsb). I/O O BA1:0 Bank Address supporting up to 4 internal banks. O RAS Row Address Strobe. O CAS Column Address Strobe. O DQM0:3 DQM for byte lane: 0 (MemData00:7), 1 (MemData08:15), 2 (MemData16:23), and 3 (MemData24:31) O BankSel0:1 Select up to two external SDRAM banks. O WE Write Enable. O ClkEn0:1 SDRAM Clock Enable. O MemClkOut0:1 External Slave Peripheral Interface PerData00:15 PerAddr03:05 PerAddr06:31 PerWBE0:1 [PerWE] Two copies of an SDRAM clock allows, in some cases, glueless SDRAM attach without requiring this signal to be repowered by a PLL or zero-delay buffer. Peripheral data bus. Note: PerData00 is the most significant bit (msb) on this bus. Peripheral address bus. Note: PerAddr03 is the most significant bit (msb) on this bus. These pins act as byte-enables which are valid for an entire cycle or as write-byte-enables which are valid for each byte on each data transfer, allowing partial word transactions. Peripheral write enable. Low when either of the two PerWBE0:1 write byte enables are low. To access this function, software must toggle a DCR bit. PerCS0 Peripheral chip select bank 0. O [PerCS1:4] Four additional peripheral chip selects To access this function, software must toggle a DCR bit. O I/O I/O O O O 1 1 7 7 1, 7 3/19/03 35

Signal Functional Description (Part 4 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See External Bus Control Signals on page 32. Signal Name Description I/O Type Notes PerOE Peripheral output enable. O PerR/W Peripheral read/write. High indicates a read from memory, low indicates a write to memory. PerReady Ready to transfer data. I [PerBLast] Used to indicates the last transfer of a memory access. To access this function, software must toggle a DCR bit. PerClk Peripheral clock to be used by peripheral slaves. O ExtReset Peripheral reset to be used by peripheral slaves. O Internal Peripheral Interface UART0_Rx UART0 Serial Data In. I UART0_Tx UART0 Serial Data Out. O [UART0_DCD] [UART0_DSR] UART0 Data Carrier Detect. To access this function, software must toggle a DCR bit. UART0 Data Set Ready. To access this function, software must toggle a DCR bit. UART0_CTS UART0 Clear To Send. I [UART0_DTR] UART0 Data Terminal Ready. To access this function, software must toggle a DCR bit. UART0_RTS UART0 Request To Send. O [UART0_RI] [UART1_Rx] [UART1_Tx] UART0 Ring Indicator. To access this function, software must toggle a DCR bit. UART1 Serial Data In. To access this function, software must toggle a DCR bit. UART1 Serial Data Out. To access this function, software must toggle a DCR bit. O I/O I I O I I O IICSCL IIC Serial Clock. I/O 3.3V IIC 1, 2 IICSDA IIC Serial Data. I/O 3.3V IIC 1, 2 Interrupts Interface [IRQ0:6] Interrupt requests To access this function, software must toggle a DCR bit. I 7 1 1, 7 1 6 1 1 1 6 1 1 1 36 3/19/03

Signal Functional Description (Part 5 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See External Bus Control Signals on page 32. Signal Name Description I/O Type Notes JTAG Interface TDI Test data in. I TMS JTAG test mode select. I TDO Test data out. O TCK TRST System Interface SysReset JTAG test clock. The frequency of this input can range from DC to 25MHz. JTAG reset. TRST must be low at power-on to initialize the JTAG controller and for normal operation of the PPC405EP. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an opendrain output (two states; 0 or open circuit). SysErr Set to 1 when a Machine Check is generated. O Halt Halt from external debugger. I GPIO00:31 TestEn General Purpose I/O. All of the GPIO signals are multiplexed with other signals. Test Enable. Used only for manufacturing tests. Pull down for normal operation. I I I/O I/O I 1.8V CMOS w/pull-down SysClk Main system clock input. I [RejectPkt0:1] External request to reject a packet. I AV DD Clean voltage input for the PLL. I A Clean Ground input for the PLL. I 1, 4 1, 4 1, 4 5 1, 2 6 1, 2 1 3/19/03 37

Trace Interface [TS1E] [TS2E] [TS1O] [TS2O] Signal Functional Description (Part 6 of 6) Secondary multiplexed signals are shown in brackets. Notes: 1. Receiver input has hysteresis. 2. Must pull up. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 3. Must pull down. See Pull-Up and Pull-Down Resistors on page 31 for recommended termination values. 4. If not used, must pull up. 5. If not used, must pull down. 6. Strapping input during reset; pull up or pull down as required. 7. Pull-up may be required. See External Bus Control Signals on page 32. Power Signal Name Description I/O Type Notes Other pins [TS3:6] [TrcClk] Even Trace execution status. To access this function, software must toggle a DCR bit Odd Trace execution status. To access this function, software must toggle a DCR bit Trace status. To access this function, software must toggle a DCR bit Trace interface clock. Operates at half the CPU core frequency. To access this function, software must toggle a DCR bit Note: Initialization strapping must hold this pin low (0) during reset. Ground Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are also thermal balls. O O O O na na na Output driver voltage 3.3V. na na na V DD Logic voltage 1.8V. na na na 1 1 1 1 Reserved Reserved pins. Do not make voltage, ground, or signal connections to these pins. na na na 38 3/19/03

Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings. Characteristic Symbol Value Unit Supply Voltage (Internal Logic) V DD 0 to +1.95 V Supply Voltage (I/O Interface) 0 to +3.6 V PLL Supply Voltage AV DD 0 to +1.95 V Input Voltage (1.8V CMOS receivers) V IN 0 to +1.95 V Input Voltage ( receivers) V IN 0 to +3.6 V Input Voltage (5.0V LVTTL receivers) V IN 0 to +5.5 V Storage Temperature Range T STG -55 to +150 C Case temperature under bias T C -40 to +120 C Note: All specified voltages are with respect to. Package Thermal Specifications The PPC405EP is designed to operate within a case temperature range of -40 C to +85 C. Thermal resistance values for the E-PBGA packages in a convection environment are as follows: Package Thermal Resistance Symbol Airflow ft/min (m/sec) Unit 0 (0) 100 (0.51) 200 (1.02) 31mm, 385-balls Junction-to-Case θ JC 2 2 2 C/W 31mm, 385-balls Case-to-Ambient 1 θ CA 17.8 16.8 16.1 C/W Note: 1. For a chip mounted on a JEDEC 2S2P card without a heat sink. 2. For a chip mounted on a card with at least one signal and two power planes, the following relationships exist: a. Case temperature, T C, is measured at top center of case surface with device soldered to circuit board. b. T A = T C P θ CA, where T A is ambient temperature and P is power consumption. c. T CMax = T JMax P θ JC, where T JMax is maximum junction temperature and P is power consumption. 3/19/03 39