8M x 64 Bit PC-100 SDRAM DIMM

Transcription

1 PC-100 SYNCHRONOUS DRAM DIMM 64814ESEM4G09TWF 168 Pin 8Mx64 (Formerly 64814ESEM4G09T) Unbuffered, 4k Refresh, 3.3V with SPD Pin Assignment General Description The module is a 8Mx64 bit, 9 chip, 168 Pin DIMM module consisting of (8) 2Mx8x4 (TSOP) SDRAM and (1) 256x8 EEPROM for serial presence detect. The module conforms to PC-100 specifications, is unbuffered, and has byte data masks. Features Fully PC-100 Compliant JEDEC-Standard 168-pin Dual Inline Memory Module (DIMM) Unbuffered PC-100 CAS Latency 2 Based on 8Mx8 SDRAM Components Power Supply: 3.3V ± 0.3V 64ms, 4096-cycle refresh Serial Presence Detect (SPD) LVTTL Compatible Inputs and Outputs One External Bank Four Internal Banks Pure Power and Ground Planes Gold PCB connector Pin# Pin# Pin# Pin# 1 Vss 85 Vss 43 Vss 127 Vss 2 DQ0 86 DQ32 44 NC 128 CKE0 3 DQ1 87 DQ33 45 S2* 129 NC 4 DQ2 88 DQ34 46 DQMB2 130 DQMB6 5 DQ3 89 DQ35 47 DQMB3 131 DQMB7 6 Vcc 90 Vcc 48 NC 132 NC 7 DQ4 91 DQ36 49 Vcc 133 Vcc 8 DQ5 92 DQ37 50 NC 134 NC 9 DQ6 93 DQ38 51 NC 135 NC 10 DQ7 94 DQ39 52 NC 136 NC 11 DQ8 95 DQ40 53 NC 137 NC 12 Vss 96 Vss 54 Vss 138 Vss 13 DQ9 97 DQ41 55 DQ DQ48 14 DQ10 98 DQ42 56 DQ DQ49 15 DQ11 99 DQ43 57 DQ DQ50 16 DQ DQ44 58 DQ DQ51 17 DQ DQ45 59 Vcc 143 Vcc 18 Vcc 102 Vcc 60 DQ DQ52 19 DQ DQ46 61 NC 145 NC 20 DQ DQ47 62 NC 146 NC 21 NC 105 NC 63 NC 147 NC 22 NC 106 NC 64 Vss 148 Vss 23 Vss 107 Vss 65 DQ DQ53 24 NC 108 NC 66 DQ DQ54 25 NC 109 NC 67 DQ DQ55 26 Vcc 110 Vcc 68 Vss 152 Vss 27 WE* 111 CAS* 69 DQ DQ56 28 DQMB0 112 DQMB4 70 DQ DQ57 29 DQMB1 113 DQMB5 71 DQ DQ58 30 S0* 114 NC 72 DQ DQ59 31 NC 115 RAS* 73 Vcc 157 Vcc 32 Vss 116 Vss 74 DQ DQ60 33 A0 117 A1 75 DQ DQ61 34 A2 118 A3 76 DQ DQ62 35 A4 119 A5 77 DQ DQ63 36 A6 120 A7 78 Vss 162 Vss 37 A8 121 A9 79 CK2 163 CK3 38 A10/AP 122 BA0 80 NC 164 NC 39 BA1 123 A11 81 WP 165 SA0 40 Vcc 124 Vcc 82 SDA 166 SA1 41 Vcc 125 CK1 83 SCL 167 SA2 42 CK0 126 NC 84 Vcc 168 Vcc * Active Low 1

2 Block Diagram 64, 1BANK with 8 SDRAM S0 DQMB0 DQMB4 DQ(0:7) U1 DQ(32:39) U5 DQMB1 DQMB5 DQ(8:15) U2 DQ(40:47) U6 S2 DQMB2 DQMB6 DQ(16:23) U3 DQ(48:55) U7 DQMB3 DQMB7 DQ(24:31) U4 DQ(56:63) U8 RAS RAS : SDRAMs U1 - U8 CAS CAS : SDRAMs U1 - U8 WE WE : SDRAMs U1 - U8 A0 - A12 A0 - A12 : SDRAMs U1 - U8 BA0, BA1 BA0, BA1 : SDRAMs U1 - U8 CLOCK INPUT *CK0 *CK1 *CK2 *CK3 *CLOCK WIRING SDRAM 4 SDRAM TERMINATION 4 SDRAM TERMINATION * wire per Clock loading Table/Wiring diagrams. CKE0, CKE1 SDRAMs U1 - U8 Bypass: Two 0.33uF and One 0.10uF capacitor per SDRAM device. SCL SERIAL PD A0 A1 A2 SA0 SA1 SA2 47K SDA WP VCC U1 - U8 VSS U1 - U8 NOTE: ALL RESISTOR NETWORK VALUES ARE 10 OHMS. 2

3 Pin Descriptions Pin Name Function # System Clock All input signals are sampled on the rising edge of clock. S# Chip Select Enables and disables the command decoder. All commands are disabled when S# is high. CKE Clock Enable Masks system clock to freeze current operation on the next clock cycle, also provides access to standby mode (see truth table). A# Address Lines Input lines for Row/Column address. BA# Bank Select Lines Selects the internal bank to be accessed during a row or column address latch. RAS Row Address Strobe Latches the row address on the rising edge of clock when asserted. CAS Column Address Strobe Latches the column address on the rising edge of clock when asserted. WE Write Enable Enables write operation and row precharge. DQM0-DQM7 Data Masks Provides a byte mask for write operations and a byte enable for read operations. DQ0-DQ63 Data Lines Data input/output lines. Vdd Power Supply Power Supply 3.3V±0.3V Vss Ground Ground WP SPD Write Protect Serial Presence Detect (SPD) EEPROM write protect. SPD programming is inhibited when asserted. SDA, SCL SPD Data/Clock Lines Serial Presence Detect (SPD) EEPROM bus lines. These line provides bi-direcitonal data transfer over an I 2 C bus. SA0 SA2 SPD Address Lines Serial Presence Detect (SPD) EEPROM address lines. These lines are used to configure the SPD. NC No Connection Line is not connected in DIMM. 3

4 Serial Presence Detect Matrix Byte # Function Binary Hex Description MS-LS 0 Define # of bytes written into EEPROM Total # of bytes of SPD memory device Fundamental memory type (EDO,SDRAM...) SDRAM 3 # of row addresses C 12 4 # of column addresses # of module rows Data width Data width continued Voltage interface LVTTL 9 SDRAM cycle time ns 9 SDRAM cycle time A0 10ns 10 SDRAM access from clock ns 11 DIMM configuration type (non-parity,ecc ) non-parity 12 Refresh rate/type Normal/Self 13 Primary SDRAM width Error checking SDRAM width Minimum clock delay back to back random column address Burst lengths supported F page/8/4/2/1 17 # of banks on each SDRAM device CAS# latencies supported /2 18 CAS# latencies supported CS# latency CS latency=0 20 Write latency WE latency=0 21 SDRAM module attributes Unbuffered 22 SDRAM device attributes: general E Write1/Read burst/precharge 23 Min SDRAM cycle time at CL A0 10ns 23 Min SDRAM cycle time at CL C0 12ns 24 SDRAM access from clock at CL ns 24 SDRAM access from clock at CL ns 25 Min SDRAM cycle time at CL Max SDRAM access from clock at CL Min row precharge time ns 28 Min row active to row active ns 29 Min RAS to CAS delay ns 30 Minimum RAS pulse width ns 31 Density of each row on module MB 32 Command and Address signal input setup time ns 33 Command and Address signal input hold time ns 34 Data signal input setup time ns 35 Data signal input hold time ns Superset information (may be used in future) Not written 62 SPD data revision code Checksum for bytes 0-62 xxxxxxxx Manufacturer's information Not written 126 Intel specification frequency Mhz 127 Intel specification CAS# latency support CAS latency Unused storage locations Not written NOTE: 1. x = Variable Data. 4

5 Simplified Truth Table 8M x 64 Bit PC-100 Command CKEn-1 CKEn S* RAS* CAS* WE* DQM BA0,1 A10/AP A11 A9-A0 Note Register Mode Register Set H L L L L OP Code 1 Refresh Auto refresh H H L L L H Entry L Self H Refresh Exit L H L H H H Bank active & row address H L L H H V Row Address Read & column Auto precharge disable L Column addr H L H L H V address Auto precharge enable H (A0-A8) 2 Write & column Auto precharge disable L Column addr H L H L L V address Auto precharge enable H (A0-A8) 2 Burst stop H L H H L Precharge Bank Selection V L H L L H L All Banks H Clock Suspend Mode or Entry H L active power down Exit L H Precharge power down mode Entry H L H L H H H Exit L H H L V V V DQM H V 3 No operation command H L H H H (V=Valid, =Don t care, H=Logic High, L=Logic Low) Notes: 1. MRS can be issued only in idle state. 2. A burst read or write with auto precharge cannot be interrupted. New commands can be issued t RP after the end of the burst. 3. DQM sampled on positive clock edge results in Hi-Z within 2 cycles, however data is immediately invalid and should be ignored. 5

6 Absolute Maximum Ratings Parameter Symbol Value Units Voltage on any pin relative to Vss V in -1.0 to 4.6 V Short circuit output current I out 50 ma Power dissipation Pt 9 W Operating temperature T opr 0 to +70 C Storage temperature T st -55 to +125 C 8M x 64 Bit PC-100 NOTE: Permanent damage may occur if absolute maximum ratings are exceeded. Device should be operated within recommended operating conditions only. DC Characteristics (T A = 0 to 70C, Vcc = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Units Note Supply voltage Vss V Supply voltage Vcc V Input high voltage Vih Vcc+0.3 V 1 Input low voltage Vil V 2 Output high voltage Voh V Ioh=-2mA Output low voltage Vol V Iol=2mA Leakage Current DQm.CBm µa SDA,SCL, µa SAm,CKEm CKm,Sm Iil µa RAS*,CAS*, WE*,Am,BA µa DQMBm µa DC Current Consumption (T A = 0 to 70C, Vcc = 3.3V ± 0.3V) Parameter Symbol Test Condition CL2 Unit Note Operating Current I CC1 Burst Length = 1, t RC > t RC (min), I OL = 0 ma 1040 ma 3, 4 Operating Current, Burst mode I CC4 BL = 4, I OL= 0Ma, Tck = Min 1680 ma 3, 4, 5 Refresh Current, 4K refresh I CC5 t RC > t RC (min) 1200 ma 3 Self Refresh Current I CC6 CKE < 0.2 V 4.5 ma 3 CL : CAS Latency Capacitance (T A = 0 to 70C, Vcc = 3.3V ± 0.3V, Vss = 0V) Parameter Symbol Typ Max Units Note Input capacitance (Am, BA0,CKEm) C I1-38 pf Input capacitance (DQMBm) C I2-4 pf Input capacitance (CAS*, RAS*, WE*) C I3-38 pf Input capacitance (CKm) C I4-10 pf Input capacitance (SDA,SCL,SAm) - 10 pf Input/Output capacitance (DQm,CBm) C I/O - 4 pf 6

7 AC Characteristics (T A = 0 to 70C, Vcc = 3.3V ± 0.3V, Vss = 0V) Parameter Symbol - 8 (PC100) Cycle time CL=3 t CK 8 - ns 10 Cycle time CL=2 t CK 10 - ns 10 high pulse width t CH 3 - ns to valid output delay CL=3-6 ns 13 to valid output delay CL=2-6 ns 13 Output data hold time 3 - ns Output valid to High-Z CL=3 t HZ - 6 ns 5 Output valid to High-Z CL=2 t HZ - 6 ns 5 low pulse width t CL 3 - ns Command setup time 2 - ns Address setup time t AS 2 - ns Clock enable setup time 2 - ns Data input setup time t DS 2 - ns Command hold time 1 - ns Address hold time t AH 1 - ns Clock enable hold time t CKH 1 - ns Data input hold time 1 - ns Power down exit setup time t PDE 1 - ns to output in Low-Z t LZ 1 - ns Row active to Row active delay t RRD (min) 16 - ns RAS* to CAS* delay t RCD (min) 20 - ns Row precharge time t RP (min) 20 - ns Row active time t RAS ns Row cycle time t RC (min) 68 - ns Mode Register set to Active Delay t RSC (min) 2 - ns Refresh Period 4096 ( rows) t REF 64 ms Auto Refresh Period t RFC 70 ns Transition Time t T ns 14 WRITE Recovery Time t WR 15 ns 12 Exit Self Refresh to Active Command t SR 80 - ns 9 CL : CAS Latency Min Notes : 1. Overshoot: Vih (MA) = Vdd + 2.0V for 10ns 2. Undershoot: Vil (MIN) = 2.0V for 10ns 3. I DD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. t HZ defines the time at which the output achieves the open circuit condition; it is not a reference to V oh or V ol. The last valud data element will meet before going High-Z. 6. Other input signal s are allowed to transition no more than once every two clocks and are otherwise at valid V ih or V il levels. 7. The I DD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 8. Address transitions average one transition every two clocks. 9. must be toggled a minimum of two times during this period. 10. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints spedified for the clock pin) during access or precharge states (READ, WRITE, including t WR, and PRECHARGE commands). CKE may be used to reduce the data rate. 11. Auto precharge mode only. The precharge timing budget (t RP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 12. Precharge mode only. 13. at CL=3 with no load is 4.6ns and is guaranteed by design. 14. t CK=7.5ns 15. AC characteristics assume t T = 1ns. Timings listed are for discrete SDRAM components. Max Units Note 7

8 Command Input Timing t CK t CL t CH V IH V IL t T t T CS RAS CAS WE t AS t AH A0-A11 BS0,1 t t CKH CKS t CKH t CKH CKE Read Timing Read CAS Latency CS RAS CAS WE A0-A1 BS0,1 t HZ DQ Read Command t LZ Burst Length 8

9 Control Timing of Input Data (Word Mask) DQM t DS t DS t DS tds DQ0~7 (Clock Mask) t CKH t CKH CKE t tds DH t t DS DS tds DQ0~7 Control Timing of Output Data (Output Enable) DQM t HZ t LZ DQ0~7 (Clock Mask) t CKH t CKH CKE DQ0~7 9

10 Mode Register Set Cycle t RSC CS RAS CAS WE A0 to A10 BS t AS t AH Register Set Data Next Command 10

11 OUTLINE DRAWING Front Side SIDE VIEW Back Side.160 Note: Drawing is for component location only, assembly may not have all components installed. 11