Assertion and Model Checking of SystemC

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Assertion and Model Checking of SystemC Sofiène Tahar Hardware Verification Group Department of Electrical and Computer Engineering Concordia University Montreal, Quebec, CANADA First Annual North American SystemC Users Group (NASCUG) Meeting June 07, 2004

2 Outline SystemC Verification: State-of-the-art Proposed Verification Approach Model Checking Assertion Based Verification Conclusion

SystemC Verification Problematic SystemC Verification: Functional verification of SoC design (in particular SW) is difficult. Checking each feature/subsystem separately is not enough to ensure correct operation. Verifying SystemC under construction only makes things worse: adding HW/SW immaturity issues. State-of-the-art: No relevant new techniques. Adapting existing methodologies using: Assertion based verification (ABV). Model checking. Guiding test vector generation (functional coverage).

Proposed Solution for SystemC Verification SystemC Code Entry Point Guide the Abstraction Disjunctive Static Code Type Analyzer Entry Branch Reduced Distribution Reduced Point Hypergraph Conjunctive Hypergraph Type to ASM Hypergraph Distribution Branch PSL (ASM) to C# Confined ASM to FSM Hypergraph Assertions Junction Type Verifier PSL Junction Model Branch Checker Junction Point Output Type Test Bench Generator Output Branch Output Point USER Properties Test Benches Assertions

Case Study: Bus Structure Master1 Master2 Master3 Clock Bus Arbiter Slave 1 Slave 2

Snapshot of the Hypergraph EventsStack, EnventManager master_direct.main_action() fast_memory.main_action() [ ] clk 1 0 0 slow_memory.main_action() arbiter.arbitrate() Event s Environment master_blocking.main_action() sbus.main_action() master_nonblock.main_action() 0 master1 master3 Stack, Env Simulation Manager master2 arbiter sbus l 1 [ ] ( ) l 2 ( ) Id 1 Id P Program Environment slave1 slave2 l 3

Static Code Analysis Static code analysis: Verify some properties statically. Simplify the system structure. Offer an interactive and graphical platform. Hypergraph statically executed: Extract a reduced representation. Verify some of the system s properties (infinite loops, etc.) Reduced hypergraph: Translated to a format supported by the model checker. Used in abstract debugging. Executed to get simplified graphical snapshots of the system during execution.

Model Checking: A Simple Approach SystemC Code Guide the Abstraction Static Code Analyzer Hypergraph to ASM USER PSL (ASM) to C# ASM to FSM Assertions Verifier PSL Model Checker Properties Test Bench Generator Test Benches Assertions

Model Checking: A Simple Approach SystemC Design Abstraction Library Static Code Analyzer Reduced Hypergraph Hypergraph to Verilog Converter Design in Verilog USER Model Checker (FormalCheck) User Defined Properties Verification terminates (property verified or failed) or never terminates (state explosion)

Model Checking: An ASM Based Approach SystemC Code Guide the Abstraction Static Code Analyzer Hypergraph to ASM USER PSL (ASM) to C# ASM to FSM Assertions Verifier PSL Model Checker Properties Test Bench Generator Test Benches Assertions

Model Checking: An ASM Based Approach SystemC Design PSL Property C++ Compiler Assertion Parser Hypergraph Generator Hypergraph to ASM Translator ASM/PSL Property Generator PSL Semantics (ASM) Design Modeled in ASM SystemC Simulator Semantics (ASM) AsmL Tool (AsmL Compiler) PSL Property Modeled in ASM System s FSM FSM to Model Checker Input Language Translator Model Checker

Assertion Based Verification (ABV) SystemC Code Static Code Analyzer Reduced Hypergraph. User s Assertions Assertions Verification ABV integration on top of SystemC: External monitors: easy to integrate and re-use. Start with SystemVerilog Assertion (SVA) then extend to Sugar s assertions. ABV Verification: Need to abstract the system and apply heuristic algorithms. Needs good coverage. Requires guiding the test vector s generation. Yields very large system state space.

ABV: A Simple Approach SystemC Code Guide the Abstraction Static Code Analyzer Hypergraph to ASM USER PSL (ASM) to C# ASM to FSM Assertions Verifier PSL Model Checker Properties Test Bench Generator Test Benches Assertions

ABV: A Simple Approach SystemC Design Assertion in SVA Format GCC Compiler Table of Symbols Assertion validation Assertion compiler Updated Design Design Updater List of Updates Assertion Monitor Assertion Integrator SystemC updated design containing the assertion s monitor

ABV: An Enhanced Approach SystemC Code Assertion Hypergraph Generation Reduced Hypergraph Dependency Check Test Program Generator 1. Dependency Relations 2. Inputs Ranges DNA Evaluation Initial DNA Generation DNA Update Final Generator s DNA

ABV: An ASM Based Approach SystemC Code Guide the Abstraction Static Code Analyzer Hypergraph to ASM USER PSL (ASM) to C# ASM to FSM Assertions Verifier PSL Model Checker Properties Test Bench Generator Test Benches Assertions

ABV: An ASM Based Approach SystemC design GCC compiler Table of symbols List of updates PSL Assertion Assertion Parser Design updater Updated design ASM/PSL Property Generator AsmL Tool (AsmL Compiler) PSL Semantics (ASM) Assertion integrator PSL Assertion in C# SystemC updated design containing the assertion s monitor

Related Work Finite-state verification of software: JAVA: BANDERA [Kansas University]: provides support for the extraction of safe, compact, finite-state models suitable for verification. C: SLAM [Microsoft], BLAST [University of Berkeley], etc. Static code analysis of object-oriented languages: [Ferdinand 96]: Abstract debugging. OO languages abstraction: [Chambers 90] : stack allocation and synchronization (Java programs) [Vederine 00] : a platform for total analysis (both C++ and ML).

Case Study: Bus Structure Master1 Master2 Master3 Clock Bus Arbiter Slave 1 Slave 2

Property 1: Property 2: Property 3: Bus Verification NEVER( (simple_bus.request == true) && (simple_bus.status!= Bus_OK) ) AFTER( (simple_bus.request == true) && (simple_bus.request.block == Bus_OK) ) EVENTUALLY (simple_bus.status == BUS_BLOCK) EVENTUALLY (simple_bus.status == BUS_OK) Direct verification using FormalCheck: failed to complete after few minutes with out of memory problem!

Snapshot of the Hypergraph EventsStack, EnventManager master_direct.main_action() fast_memory.main_action() [ ] clk 1 0 0 slow_memory.main_action() arbiter.arbitrate() Event s Environment master_blocking.main_action() sbus.main_action() master_nonblock.main_action() 0 master1 master3 Stack, Env Simulation Manager master2 arbiter sbus l 1 [ ] ( ) l 2 ( ) Id 1 Id P Program Environment slave1 slave2 l 3

Experimental Results The main reductions concern: Transforming the SystemC simulator into a while loop. Reducing the packet to its packet header. Reducing some of the variables sizes. Property P1 P2 P3 CPU Time 6:59:12 15:23:02 17:46:54 Memory (in MB) 93.59 183.91 293.63

Assertion 1: Assertions Definition assert property1 @ (posedgeclk) (st == ack) && (flag == 1)!req[*8]) Assertion 2: assert property2 @(posedgeclk) (simple bus.request == true) && (master1.active master2.active master3.active) Assertion 3: assert property3 @(posedgeclk) (simple bus.request == true) && (simple bus.request.nonblock == true) simple bus.status == BUS OK[*1])

Coverage as Function of the Generation 100 90 Coverage (in %) 80 70 60 50 40 Assertion 1 Assertion 2 Assertion 3 30 0 5 10 15 20 25 30 35 Generation

Genetic versus Random Coverage Assertion 1 Assertion 2 Assertion 3 Random Test (%) 10 8 12 Initialization of GA (%) 34 42 32 GA after 35 Iterations (%) 92 93 85 Static code analysis refines the space of possible values. GA allows to offer better coverage of the assertions (more than 90% for Assertion 1). Mutation mechanism: overcomes the local maxima problem.

ABV Monitors Output SystemC updated design containing the assertion s monitor Verification Report Exceptions or Warnings Notification Signals

Conclusion SystemC functional verification: Difficult for complex SoCs. Verification must consider IPs and their interaction. SystemC software functionality testing is inherently difficult. Need to develop SystemC verification methodologies. Our solution: combination of several techniques: Static code analysis. Model checking. Assertion based verification. Interface SystemC to existing tools through ASM semantics.

28 For any further details, visit the project webpage at: System-on-Chip Verification <http://hvg.ece.concordia.ca/research/soc/> Thanks! Hardware Verification Group 2004

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