FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011
About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level logic implementation Composed of programmable logic blocks and interconnects Some complex FPGAs also include non-programmable logic blocks (such as processor cores, MAC units, and SRAMs) to improve efficiency Platform FPGA R. H. Freeman, Configurable Electrical Circuit Having Configurable Logic Elements and Configurable Interconnect, U.S. Patent 4,870,302, Sep. 26, 1989 2/32
Electronic Logic Components Logic General Purpose IC ASIC Programmable Logic Devices Gate Arrays Cell-based ICs Full Custom ICs SPLDs (PALs) CPLDs FPGAs 3/32
Programmable Array Logic (PAL) PAL is a special case of sum-of-product logic in which the AND array is programmable and the OR array is fixed Each input is buffered and drives many AND gates: non-inverted output inverted output AND gate symbols in PAL: A B C A B C ABC ABC 4/32
Function Implementation Using PAL Combinational PALs have 10 ~ 20 inputs and 2 ~ 10 outputs; with 2 ~ 8 AND gates driving each OR gate Sequential PALs has extra D flip-flops with input driven from the programmable array logic a full adder in PAL 5/32
Complex Programmable Logic Devices If several PLDs, along with some flip-flops, are put into a single IC, we have a complex programmable logic device (CPLD) that can be used to implement a small digital system Example: Xilinx CoolRunner Macrocell (MUXs and buffers) PAL block 6/32
Field Programmable Gate Arrays The basic ideas of FPGA s is to inter-connect small truth tables to form complex digital circuits table 1 Inputs Output ABCD Q 0000 1 0001 0...... 1111 1... table 2 Inputs Output ABCD Q 0000 0 0001 1...... 1111 1 table 3 Inputs Output ABCD Q 0000 0 0001 0...... 1111 1 7/32
Logic Design with FPGA A digital design on FPGA is composed of three parts: Logic elements Interconnect I/O blocks (IOB) An FPGA configuration is similar to a program for microprocessor Specifies functional units and interconnects between functional units IOB IOB Interconnect LE LE LE LE LE LE IOB IOB IOB LE LE LE Interconnect IOB 8/32
CPU v.s. FPGA Microprocessor & FPGAs are programmed in different ways FPGA program bits memory instructions data CPU logic logic logic logic 9/32
Logic Elements Logic element (LE) is more capable than logic gates A simple LE can be programmed to behave as an n-input, m-output function (for example, n = 4, m = 1); such LE s are called fine-grained LE s (relatively speaking, these LE are coarse compared to a gate, for example) Many FPGAs include distributed register bits around the LE An FPGA may provide specialized complex LE blocks, such as multipliers, SRAMs, or processors These are all called coarse-grained LEs A platform-fpga is composed of both fine-grained and coarse-grained LEs 10/32
Generic Logic Elements Example of fine-grain logic element structure Interconnect IOB LE LE LE IOB IOB LE LE LE IOB Logic Element configuration bit IOB LE LE LE IOB Interconnect Lookup Table (LUT) D Q LE out inputs 0 0 0 0 0 0 0 1... 1 1 1 1 out 1 0 1 11/32
Function Implementation with LUT The datapath that implements F = A B C + A BC + AB is as follows, the LUT4 has entries as follows: X 1 X 2 X 3 X 4 0000 0001 0010 0011... 1111 F 0 0 1 1... 1 LUT4 table entries (red means don t care) A function with more than 4 variables can always be decomposed to the sum (OR) of 4-variable function 12/32
Carry Chains in FPGA Since addition is a very important operation, many FPGAs have a dedicated circuitry for carry bit calculation and propagation. 13/32
Example: Spartan 2 Architecture (1/2) A Xilinx Spartan device is composed of a 2-D array of Configurable Logic Blocks (CLB) 14/32
Example: Spartan 2 Architecture (2/2) In Spartan II, each CLB has two identical slices; each slice contains two logic cells with a LUT, carry logic, and a register F5IN G4 G3 G2 G1 Lookup Table COUT carry/ control logic D Q YB Y YQ BY SR F4 F3 F2 F1 Lookup Table carry/ control logic D Q XB X XQ BX CE CLK CIN 15/32
Example: Spartan 2 I/O Blocks Supports multiple I/O standards (PCI, AGP, etc.) 16/32
Logic Implementation on FPGA Logic synthesis How do we breakdown a function and map it to logic elements? How do we implement an operation within a logic element? Logic placement Where do we put each piece of logic in the array of logic elements? LE LE LE LE LE LE LE LE LE 17/32
Interconnect Architecture On an FPGA, we must be able to control Connections from wiring channels to LEs Connections between wires in the wiring channels Wiring channel LE LE channel channel channel channel 18/32
Programmable Wiring Wiring among LEs is organized into channels Channels are arranged horizontally and vertically on the chip There are many wires per channel Connections between wires made at programmable interconnection points An EDA tool must choose: Channels from source to destination Wires within the channels vertical channel 1 LE LE LE horizontal channel 2 LE LE LE vertical channel 3 LE LE LE LE LE horizontal channel 3 LE vertical channel 5 19/32
Programmable vs Fixed Interconnect Compares to the wiring of fixed layout in a custom logic, there are two major disadvantages of FPGA interconnect: Switch adds delay D Q FPGA interconnect has extra length The problem becomes worse as the logic becomes larger 20/32
Interconnect Strategies Types of wires: Short wires: local LE connections Global wires: long-distance, buffered communication Special wires: clocks, etc Use design hierarchy to guide placement search Use hard macros where possible A macro is a larger modules designed to fit into a particular FPGA (similar to IP blocks for platform-based SoC) Hard macro includes placement Soft macro does not include placement Add placement constraints 21/32
FPGAs and I/O Pins Chip capacity is growing faster than package pinout Now, we can put many hardware functions in an FPGA, but the total number of I/O pins is limited Must try to share a small amount of interface pins among functions Alternatively, one can use multiple smaller FPGAs to compose same functions It s harder to breakdown a design across FPGAs The performance may be better due to shorter routing lengths 22/32
FPGA Configuration Technologies FPGA s logic elements, interconnect switch, and I/O pins can be programmed using one of the following three technologies: SRAM-based Can be programmed many times Must be programmed after power-up Antifuse-based Programmed once via a burn-in step Flash-based Similar to SRAM but using flash memory 23/32
SRAM-based FPGAs Program logic functions and interconnect using SRAM to store boolean table and on/off state Advantages: Re-programmable dynamically reconfigurable uses standard processes Disadvantages: SRAM burns power Configuration lost at power-down (but not on reset!) Possible to steal, disrupt configuration bits Just like piracy & virus issues of software 24/32
Configuring SRAM-based FPGA There are several ways to configure an FPGA JTAG interface, not good for turn-key systems FPGA in master mode, read configuration data from PROM FPGA in slave mode, microcontroller configures an FPGA 25/32
Features of SRAM-based LUT n-input LUT can handle function of 2 n inputs All logic functions take the same amount of space All functions have the same delay With CMOS custom logic, XOR is much slower than NAND; with SRAM LUT, XOR is as fast (slow) as NAND SRAM is larger than static gate equivalent of function Gate-count is not a good measure for FPGA logic cost For static gate, n input NAND/NOR gate has 2n transistors For FPGA LE, 4-input LUT has 128 transistors in SRAM, 96 in multiplexer Burns power even at idle 26/32
Platform FPGAs A complex system must be composed of hardware and software components To reduce system development/integration time, some chip companies starts to push Platform FPGA visions Two examples: Xilinx has Virtex II Pro that provides PowerPC-based platform FPGA Altera has Excalibur that features ARM-based platform FPGA (a.k.a. System-on-Programmable-Chip, SoPC) 27/32
Xilinx Platform FPGA Vision Processing Platform: PowerPC D/I Caches Controllers Interfaces DSP Platform: Distributed RAM 18 18 Multipliers 600 Billion MACs/sec Connectivity Platform: 100+ Gb Bandwidth I/O interfaces of the chip Rocket I/O (3.125 Gbps serial port) Hi-speed parallel 28/32
Four Generations of Virtex Devices XC2000-XC3000 XC4000, Virtex Virtex-II Virtex-II Pro, Virtex-4, Virtex-5 Device Complexity System-Level Function Blocks Platform FPGA Platform for Programmable Systems Glue Logic 1985 1992 2000 2002 29/32
Example: Platform FPGA Systems A platform implementation with remote configuration capabilities K. Park and H. Kim, Remote FPGA Reconfiguration Using MicroBlaze or PowerPC Processors, XApp 441, Sep. 30/32006
FPGA Implementation Process Step1: Design Design entry methods: HDL (Verilog or VHDL) or schematic drawings Step 2: Create netlist (synthesis) Translates V, VHD, SCH files into the standard format EDIF file Step 3: Physical design (Implementation) Translate, map, place & route the netlist into the target device configuration bits Step 4: Configure the FPGA Download BIT file into the FPGA 31/32
FPGA Design Flow In this class, Xilinx ISE Foundation is used as the Logic design toolchain Specification Design Entry timing constraints Testbench Simulation Synthesis Mapping Static timing analysis Place & Route bit file FPGA 32/32