CSE 533: Advanced Computer Architectures Pipelining Instructor: Gürhan Küçük Yeditepe University Lecture notes based on notes by Mark D. Hill and John P. Shen Updated by Mikko Lipasti
Pipelining Forecast Big Picture Datapath Control Data Hazards Stalls Forwarding Control Hazards Exceptions 2
Motivation Instructions Program (code size N) Cycles Instruction Single cycle implementation X (CPI) Time Cycle CPI = Cycle = imem + RFrd + ALU + dmem + RFwr + muxes + control E.g. 500+250+500+500+250+0+0 = 2000ps Time/program = N x 2ns X (cycle time) 3
Idea! We use 500 MHz clock with 2ns cycle time But, we can reduce cycle time and divide the task into several stages so we can speed things up i.e. 0.5ns cycle time => 2 GHz clock 4
Multicycle Multicycle implementation: Cycle: Instr: i i+ i+2 i+3 i+4 F 2 D 3 X 4 5 M W 6 F 7 D 8 X 9 F 0 D X 2 M 3 F 5
But Multicycle implementation CPI = 3, 4, 5 Cycle = max(memory, RF, ALU, mux, control) =max(500,250,500) = 500ps Time/prog = N x 4 x 500 = N x 2000ps = N x 2ns Would like: CPI = + overhead from hazards (later) Cycle = 500ps + overhead In practice, ~3x improvement 6
Big Picture Instruction latency = 5 cycles Instruction throughput = /5 instr/cycle CPI = 5 cycles per instruction Instead Pipelining: process instructions like a lunch buffet ALL microprocessors use it E.g. Pentium-IV, Athlon, Power4 7
Big Picture Instruction Latency = 5 cycles (same) Instruction throughput = instr/cycle CPI = cycle per instruction CPI = cycle between instruction completion = 8
Ideal Pipelining L Comb. Logic n Gate Delay BW = ~(/n) L n -- 2 Gate Delay L n -- 2 Gate Delay BW = ~(2/n) L n -- Gate 3 Delay L n -- Gate 3 Delay L n -- Gate 3 Delay BW = ~(3/n) Bandwidth increases linearly with pipeline depth Latency increases by latch delays 9
Ideal Pipelining Cycle: Instr: i i+ i+2 i+3 i+4 F 2 D F 3 X D F 4 5 6 7 8 9 M W X M W D X M W F D X M W F D X M W 0 2 3 0
Pipelining Idealisms Uniform subcomputations Can pipeline into stages with equal delay Identical computations Can fill pipeline with identical work Independent computations No relationships between work units Are these practical? No, but can get close enough to get significant speedup
Complications Datapath Five (or more) instructions in flight Control Must correspond to multiple instructions Instructions may have data and control flow dependences (coming up!) i.e. units of work are not independent One may have to stall and wait for another 2
An Example Consider an unpipelined machine. Assume that it has 20 ns clock and that it uses cycles for execution frequency ALU 2 30% Branch 5 20% Memory 7 50% Suppose that due to clock skew and setup, pipelining the machine adds 2 ns overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline? 3
Datapath (Fig. 6.) 4
What Is Pipelining MIPS Datapath Without Pipelining 5
Pipelined Datapath Start with single-cycle datapath Pipelined execution Assume each instruction has its own datapath But each instruction uses a different part in every cycle Multiplex all on to one datapath Latches separate cycles (like multicycle) Ignore hazards for now Data Control Instruction PC 4 Address 0 M u x Add memory IF/ID ID/EX EX/MEM MEM/WB Instruction Read register Read register 2 isters Write register Write data Read data Read data 2 Shift left 2 0 M u x Add Add result Zero ALU ALU result Address Write data Data memory Read data M u x 0 6 Sign extend 32 6
Pipelined Datapath 0 M u x IF/ID ID/EX EX/MEM MEM/WB Add 4 Shift left 2 Add Add result PC Address Instruction memory Instruction Read register Read data Read register 2 isters Read data 2 Write register Write data 0 M u x Zero ALU ALU result Address Write data Data memory Read data M u x 0 6 Sign extend 32 7
The Basic Pipeline For MIPS Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 I n s t r. Ifetch Ifetch ALU DMem ALU DMem O r d e r Ifetch Ifetch ALU DMem ALU DMem 8
What Is Pipelining MIPS Functions 0 M u x 4 Add IF/ID ID/EX EX/MEM MEM/WB Shift left 2 Add Add result Passed To Next Stage IR Mem[PC] NPC PC + 4 PC Address Instruction memory Instruction Read register Read data Read register 2 isters Read data 2 Write register Write data 0 M u x Zero ALU ALU result Address Write data Data memory Read data M u x 0 6 Sign extend 32 Instruction Fetch (IF): Send out the PC and fetch the instruction from memory into the instruction register (IR); increment the PC by 4 to address the next sequential instruction. IR holds the instruction that will be used in the next stage. NPC holds the value of the next PC. 9
What Is Pipelining MIPS Functions 0 M u x 4 Add IF/ID ID/EX EX/MEM MEM/WB Add Add result Passed To Next Stage A s[ir 6..0 ] PC Address Instruction memory Instruction Read register Read data Read register 2 isters Read data 2 Write register Write data Shift left 2 0 M u x Zero ALU ALU result Address Write data Data memory Read data M u x 0 B s[ir..5 ] Imm ((IR 6 ) ##IR 6..3 6 Sign extend 32 Instruction Decode/ister Fetch Cycle (ID): Decode the instruction and access the register file to read the registers. The outputs of the general purpose registers are read into two temporary registers (A & B) for use in later clock cycles. We extend the sign of the lower 6 bits of the Instruction ister. 20
What Is Pipelining PC 4 Address 0 M u x Add Instruction memory IF/ID ID/EX EX/MEM MEM/WB Instruction Read register Read data Read register 2 isters Read data 2 Write register Write data MIPS Functions Passed To Next Stage If Memory Reference: ALUOutput A + Imm If - ALU Inst.: ALUOutput A func. B If -Imm ALU Inst.: ALUOutput A func. Imm If Branch: ALUOutput NPC + Imm<<2 Cond (A op 0) Execute Address Calculation (EX): We perform an operation (for an ALU) or an address calculation (if it s a load or a Branch). If an ALU, actually do the operation. If an address calculation, figure out how to obtain the address and stash away the location of that address for the next cycle. 6 Sign extend 32 Shift left 2 0 M u x Add Add result Zero ALU ALU result Address Write data Data memory Read data M u x 0 2
What Is Pipelining MIPS Functions 0 M u x 4 Add IF/ID ID/EX EX/MEM MEM/WB Shift left 2 Add Add result Passed To Next Stage If LOAD Inst: LMD Mem[ALUOutput] PC Address Instruction memory Instruction Read register Read data Read register 2 isters Read data 2 Write register Write data 0 M u x Zero ALU ALU result Address Write data Data memory Read data M u x 0 If STORE Inst: Mem[ALUOutput] B 6 Sign extend 32 MEMORY ACCESS (MEM): If this is an ALU, do nothing. If a load or store, then access memory. If this is a branch, then update PC If Branch Inst: if (Cond) PC ALUOutput else PC NPC 22
What Is Pipelining MIPS Functions 0 M u x 4 Add IF/ID ID/EX EX/MEM MEM/WB Shift left 2 Add Add result Passed To Next Stage If - ALU: s[ir 6..20 ] ALUOutput PC Address Instruction memory Instruction Read register Read data Read register 2 isters Read data 2 Write register Write data 6 Sign extend 32 0 M u x Zero ALU ALU result Address Write data Data memory Read data M u x 0 If -Imm ALU: s[ir..5 ] ALUOutput If LOAD Inst: s[ir..5 ] LMD WRITE BACK (WB): Update the registers from either the ALU or from the data loaded. 23
Things to Notice For some instructions no processing is done in certain stages: ister-to-register instructions: No process in MEM stage STORE instructions: No process in WB stage 24
Things to Notice - II Instructions may read their operands only when they are in ID stage Reason:??? 25
Things to Notice - II Instructions may read their operands only when they are in ID stage Reason: Reduces read port requirements on the ister File Complexity reduction Power/Energy reduction 26
Things to Notice - III Instructions may write their results only when they are in WB stage Reason:??? 27
Things to Notice - III Instructions may write their results only when they are in WB stage Reason: Reduces write port requirements on the ister File Complexity reduction Power/Energy reduction 28
Pipeline Hurdles Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away) Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock) Control hazards: Pipelining of branches & other instructions that change the PC Common solution is to stall the pipeline until the hazard is resolved, inserting one or more bubbles in the pipeline 29
Pipeline Hurdles Definition : Conditions that lead to incorrect behavior if not fixed Structural hazard two different instructions use same h/w in same cycle Data hazard two different instructions use same storage must appear as if the instructions execute in correct order Control hazard one instruction affects which instruction is next Resolution Pipeline interlock logic detects hazards and fixes them simple solution: stall - increases CPI, decreases performance better solution: partial stall - some instruction stall, others proceed better to stall early than late 30
I n s t r. O r d e r Structural Hazards Time (clock cycles) Load Instr Instr 2 Instr 3 Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Instr 4 Ifetch ALU Ifetch DMem ALU Ifetch DMem ALU Ifetch DMem ALU DMem ALU When two or more different instructions want to use same hardware resource in same cycle e.g., MEM uses the same memory port as IF as shown in this slide. DMem 3
Structural Hazards Time (clock cycles) I n s t r. O r d e r Load Instr Instr 2 Stall Instr 3 Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Ifetch Ifetch ALU Ifetch DMem ALU DMem ALU DMem Bubble Bubble Bubble Bubble Bubble Ifetch ALU This is another way of looking at the effect of a stall. DMem 32
Structural Hazards This is another way to represent the stall we saw on the last few pages. 33
Structural Hazards Dealing with Structural Hazards Stall low cost, simple Increases CPI use for rare case since stalling has performance effect Pipeline hardware resource useful for multi-cycle resources good performance sometimes complex e.g., RAM Replicate resource good performance increases cost (+ maybe interconnect delay) useful for cheap or divisible resources 34
Structural Hazards Structural hazards are reduced with these rules: Each instruction uses a resource at most once Always use the resource in the same pipeline stage Use the resource for one cycle only Many RISC ISA a designed with this in mind Sometimes very complex to do this. For example, memory of necessity is used in the IF and MEM stages. Some common Structural Hazards: Memory - we ve already mentioned this one. Floating point - Since many floating point instructions require many cycles, it s easy for them to interfere with each other. Starting up more of one type of instruction than there are resources. For instance, the PA-8600 can support two ALU + two load/store instructions per cycle - that s how much hardware it has available. 35
Structural Hazards This is the example on Page 44. We want to compare the performance of two machines. Which machine is faster? Machine A: Dual ported memory - so there are no memory stalls Machine B: Single ported memory, but its pipelined implementation has a.05 times faster clock rate Assume: Ideal CPI = for both Loads are 40% of instructions executed 36
Data Hazards These occur when at any time, there are instructions active that need to access the same data (memory or register) locations. Where there s real trouble is when we have: instruction A instruction B and B manipulates (reads or writes) data before A does. This violates the order of the instructions, since the architecture implies that A completes entirely before B is executed. 37
Execution Order is: Instr I Instr J Data Hazards Read After Write (RAW) Instr J tries to read operand before Instr I writes it I: add r,r2,r3 J: sub r4,r,r3 Caused by a Dependence (in compiler nomenclature). This hazard results from an actual need for communication. I r J 38
Execution Order is: Instr I Instr J Data Hazards Write After Read (WAR) Instr J tries to write operand before Instr I reads i Gets wrong operand I: sub r4,r,r3 J: add r,r2,r3 K: mul r6,r,r7 Called an anti-dependence by compiler writers. This results from reuse of the name r. Can t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5 I r J 39
Execution Order is: Instr I Instr J Data Hazards Write After Write (WAW) Instr J tries to write operand before Instr I writes it Leaves wrong result ( Instr I not Instr J ) I: sub r,r4,r3 J: add r,r2,r3 K: mul r6,r,r7 Called an output dependence by compiler writers This also results from the reuse of name r. Can t happen in MIPS 5 stage pipeline because: All instructions take 5 stages, and Writes are always in stage 5 Will see WAR and WAW in later more complicated pipes I r J 40
Data Flow Graphs I $5 I mul $5, $0, 4 I2 addu $24, $6, $5 I3 lw $25, 0($24) I4 mul $3, $24, $4 I5 addu $4, $6, $3 I6 lw $5, 0($4) $5 I2 I3 $24 $24 I4 $3 $4 I5 $4 I6 4
Data Hazards Simple Solution to RAW Hardware detects RAW and stalls Assumes register written then read each cycle + low cost to implement, simple -- reduces IPC Try to minimize stalls Minimizing RAW stalls Bypass/forward/short-circuit (We will use the word forward ) Use data before it is in the register + reduces/avoids stalls -- complex Crucial for common RAW hazards 42
Data Hazards Time (clock cycles) I n s t r. O r d e r add r,r2,r3 sub r4,r,r3 and r6,r,r7 or r8,r,r9 xor r0,r,r IF ID/RF EX MEM WB Ifetch Ifetch ALU Ifetch The use of the result of the ADD instruction in the next three instructions causes a hazard, since the register is not written until after those instructions read it. DMem ALU Ifetch DMem ALU Ifetch DMem ALU DMem ALU DMem Figure 3.9 43
Data Hazards Forwarding To Avoid Data Hazard I n s t r. add r,r2,r3 sub r4,r,r3 Time (clock cycles) Ifetch Ifetch Forwarding is the concept of making data available to the input of the ALU for subsequent instructions, even though the generating instruction hasn t gotten to WB in order to write the memory or registers. ALU DMem ALU DMem O r d e r and r6,r,r7 or r8,r,r9 Ifetch Ifetch ALU DMem ALU DMem xor r0,r,r Ifetch ALU DMem Figure 3.0 44
Data Hazards The data isn t loaded until after the MEM stage. Time (clock cycles) I n s t r. lw r, 0(r2) sub r4,r,r6 Ifetch Ifetch ALU DMem ALU DMem O r d e r and r6,r,r7 or r8,r,r9 Ifetch Ifetch ALU DMem ALU DMem There are some instances where hazards occur, even with forwarding. Figure 3.2 45
Data Hazards Time (clock cycles) The stall is necessary as shown here. I n s t r. O r d e r lw r, 0(r2) sub r4,r,r6 and r6,r,r7 Ifetch Ifetch ALU Ifetch DMem Bubble Bubble ALU DMem ALU DMem or r8,r,r9 Bubble Ifetch ALU DMem There are some instances where hazards occur, even with forwarding. Figure 3.3 46
Data Hazards This is another representation of the stall. LW R, 0(R2) IF ID EX MEM WB SUB R4, R, R5 IF ID EX MEM WB AND R6, R, R7 IF ID EX MEM WB OR R8, R, R9 IF ID EX MEM WB LW R, 0(R2) IF ID EX MEM WB SUB R4, R, R5 IF ID stall EX MEM WB AND R6, R, R7 IF stall ID EX MEM WB OR R8, R, R9 stall IF ID EX MEM WB 47
Data Hazards Pipeline Scheduling Instruction scheduled by compiler - move instruction in order to reduce stall. lw Rb, b -- code sequence for a = b+c before scheduling lw Rc, c Add Ra, Rb, Rc -- stall sw a, Ra lw Re, e -- code sequence for d = e+f before scheduling lw Rf, f sub Rd, Re, Rf -- stall sw d, Rd Arrangement of code after scheduling. lw Rb, b lw Rc, c lw Re, e Add Ra, Rb, Rc lw Rf, f sw a, Ra sub Rd, Re, Rf sw d, Rd 48
Data Hazards Pipeline Scheduling scheduled unscheduled gcc spice tex 4% 25% 3% 42% 54% 65% 0% 20% 40% 60% 80% % loads stalling pipeline 49
Control Hazards Control hazards can cause a greater performance loss for pipelines than do data hazards A control hazard occurs when we need to find the destination of a branch, and can t fetch any new instructions until we know that destination 50
Example (quicksort( quicksort/mips) # for (; (j < high) && (array[j] < array[low]) ; ++j ); # $0 = j # $9 = high # $6 = array # $8 = low bge done, $0, $9 mul $5, $0, 4 addu $24, $6, $5 lw $25, 0($24) mul $3, $8, 4 addu $4, $6, $3 lw $5, 0($4) bge done, $25, $5 cont: addu $0, $0,... done: addu $, $, - 5
Control Hazards Control Hazard on Branches Three Stage Stall 0: beq r,r3,36 Ifetch ALU DMem 4: and r2,r3,r5 Ifetch ALU DMem 8: or r6,r,r7 Ifetch ALU DMem 22: add r8,r,r9 Ifetch ALU DMem 36: xor r0,r,r Ifetch ALU DMem 52
Control Hazards Branch Stall Impact If CPI =, 30% branch, Stall 3 cycles => new CPI =.9! (Whoa! How did we get that.9???) Two part solution to this dramatic increase: Determine branch taken or not sooner, AND Compute taken branch address earlier MIPS branch tests if register = 0 or ^ 0 MIPS Solution: Move Zero test to ID/RF stage Adder to calculate new PC in ID/RF stage must be fast can't afford to subtract compares with 0 are simple Greater-than, Less-than test sign-bit, but not-equal must OR all bits more general compares need ALU clock cycle penalty for branch versus 3 In the next chapter, we ll look at ways to avoid the branch all together. 53
Control Hazards Five Branch Hazard Alternatives #: Stall until branch direction is clear #2: Predict Branch Not Taken Execute successor instructions in sequence Squash instructions in pipeline if branch actually taken Advantage of late pipeline state update 47% MIPS branches not taken on average PC+4 already calculated, so use it to get next instruction #3: Predict Branch Taken 53% MIPS branches taken on average But haven t calculated branch target address in MIPS MIPS still incurs cycle branch penalty Other machines: branch target known before outcome 54
Control Dependence One instruction affects which executes next sw $4, 0($5) bne $2, $3, loop sub $6, $7, $8 Cycle: Instr: sw F bne sub 2 D F 3 X D F 4 5 6 7 M W X M W D X M W 8 9 0 2 3 55
Control Dependence - Stall Detect dependence and stall sw $4, 0($5) bne $2, $3, loop sub $6, $7, $8 Cycle: Instr: sw F bne sub 2 3 4 5 6 D X M W F D X M W F D 2-cycle bubble 7 X 8 9 M W 0 2 3 56
Predict not taken Detect dependence and stall sw $4, 0($5) bne $2, $3, loop sub $6, $7, $8 If loop is not taken Cycle: Instr: sw F bne sub 2 D F 3 X D F 4 5 6 7 M W X M W D X M W 8 9 0 2 3 57
Control Dependence - Stall Detect dependence and stall sw $4, 0($5) bne $2, $3, loop sub $6, $7, $8 If loop is taken Cycle: Instr: sw F bne mul 2 3 4 5 6 7 8 9 D X M W F D X M W - - F D X M W SUB is flushed from the pipeline 0 2 3 58
Control Dependence - Stall Detect dependence and stall sw $4, 0($5) bne $2, $3, loop sub $6, $7, $8 If loop is taken Cycle: Instr: sw F bne mul 2 3 4 5 6 D X M W F D X M W F D 2-cycle bubble 7 X 8 9 M W 0 2 3 59
Control Hazards Five Branch Hazard Alternatives #4: Execute Both Paths #5: Delayed Branch Define branch to take place AFTER a following instruction branch instruction sequential successor sequential successor 2... sequential successor n branch target if taken Branch delay of length n slot delay allows proper decision and branch target address in 5 stage pipeline MIPS uses this 60
Control Hazards Delayed Branch Where to get instructions to fill branch delay slot? Before branch instruction From the target address: only valuable when branch taken From fall through: only valuable when branch not taken Cancelling branches allow more slots to be filled Compiler effectiveness for single branch delay slot: Fills about 60% of branch delay slots About 80% of instructions executed in branch delay slots useful in computation About 50% (60% x 80%) of slots usefully filled Delayed Branch downside: 7-8 stage pipelines, multiple instructions issued per clock (superscalar) 6
Control Hazards Evaluating Branch Alternatives Pipeline speedup = Pipeline depth +Branch frequency Branch penalty Scheduling Branch CPI speedup v. Speedup v. scheme penalty unpipelined stall Stall pipeline 3.42 3.5.0 Predict taken.4 4.4.26 Predict not taken.09 4.5.29 Delayed branch 0.5.07 4.6.3 Conditional & Unconditional = 4%, 65% change PC 62
Control Hazards Pipelining Introduction Summary Just overlap tasks, and easy if tasks are independent Speed Up Š Pipeline Depth; if ideal CPI is, then: Speedup = Pipeline Depth + Pipeline stall CPI Hazards limit performance on computers: Structural: need more HW resources Data (RAW,WAR,WAW): need forwarding, compiler scheduling Control: delayed branch, prediction X Clock Cycle Unpipelined Clock Cycle Pipelined 63
Control Hazards The compiler can program what it thinks the branch direction will be. Here are the results when it does so. Compiler Static Prediction of Taken/Untaken Branches 70% 4% Frequency of Misprediction 60% 50% 40% 30% 20% 0% 0% Misprediction Rate 2% 0% 8% 6% 4% 2% 0% alvinn compress doduc espresso gcc hydro2d mdljsp2 ora swm256 tomcatv alvinn compress doduc espresso gcc hydro2d mdljsp2 ora swm256 tomcatv Always taken Taken backwards Not Taken Forwards 64
Control Hazards Compiler Static Prediction of Taken/Untaken Branches Improves strategy for placing instructions in delay slot Two strategies Backward branch predict taken, forward branch not taken Profile-based prediction: record branch behavior, predict branch based on prior run 65
Control Hazards Evaluating Static Branch Prediction Strategies 00000 Misprediction ignores frequency of branch Instructions between mispredicted branches is a better metric Instructions per mispredicted branch 0000 000 00 0 alvinn compress doduc espresso gcc hydro2d mdljsp2 ora swm256 tomcatv Profile-based Direction-based 66
Resolution of Pipeline Hazards Pipeline hazards Potential violations of program dependences Must ensure program dependences are not violated Hazard resolution Static: compiler/programmer guarantees correctness Dynamic: hardware performs checks at runtime Pipeline interlock Hardware mechanism for dynamic hazard resolution Must detect and enforce dependences at runtime 67
Pipelined Datapath - Summary Instruction flow add and load Write of registers Pass register specifiers Any info needed by a later stage gets passed down the pipeline e.g. store value through EX 68
Pipelined Control Control Set by 5 different instructions Divide and conquer: carry IR down the pipe MIPS ISA requires the appearance of sequential execution True of most general purpose ISAs 69
Pipelined Control IF and ID None EX ALUop, ALUsrc, Dst MEM Branch, MemRead, MemWrite WB Memto, Write 70
PCSrc 0 M u x IF/ID ID/EX EX/MEM MEM/WB Add 4 Write Shift left 2 Add Add result Branch PC Address Instruction memory Instruction Read register Write data Read data Read register 2 isters Read Write data 2 register Instruction [5 0] 6 Sign 32 extend ALUSrc 0 M u x 6 ALU control Zero ALU ALU result Address Write data MemWrite Data memory MemRead Read data Memto M u x 0 Instruction [20 6] Instruction [5 ] 0 M u x ALUOp Dst 7
Figure 6.29 WB Instruction Control M WB EX M WB IF/ID ID/EX EX/MEM MEM/WB 72
Figure 6.30 PCSrc 0 M u x Control ID/EX WB M EX/MEM WB MEM/WB IF/ID EX M WB Add PC 4 Address Instruction memory Instruction Write Read register Read data Read register 2 isters Read Write data 2 register Write data Shift left 2 0 M u x Add Add result ALUSrc Zero ALU ALU result Branch Write data MemWrite Address Data memory Read data Memto M u x 0 Instruction 6 32 [5 0] Sign extend 6 ALU control MemRead Instruction [20 6] Instruction [5 ] 0 M u x Dst ALUOp 73
Pipelined Control Controlled by different instructions Decode instructions and pass the signals down the pipe Control sequencing is embedded in the pipeline 74
Pipelining Not too complex yet Data hazards Control hazards Exceptions 75
Data Hazards Must first detect hazards ID/EX.Writeister = IF/ID.Readister ID/EX.Writeister = IF/ID.Readister2 EX/MEM.Writeister = IF/ID.Readister EX/MEM.Writeister = IF/ID.Readister2 MEM/WB.Writeister = IF/ID.Readister MEM/WB.Writeister = IF/ID.Readister2 76
Data Hazards Not all hazards because Writeister not used (e.g. sw) Readister not used (e.g. addi, jump) Do something only if necessary 77
opcode dest src src2 I Data Hazards C C Hazard Detection Unit opcode dest src src2 Several 5-bit (or 6-bit) comparators Response? Stall pipeline Instructions in IF and ID stay IF/ID pipeline latch not updated Send nop down pipeline (called a bubble) PCWrite, IF/IDWrite, and nop mux I2 78
Data Hazards Data from Cache Detecting dependencies over memory locations In a typical datapath, actual writes to the main memory are serialized via write buffers Address Data to be written Writes to the Main Memory Write Buffers (FIFO) 79
Data Hazards Data from Cache Detecting dependencies over memory locations When the effective address of a LOAD is computed, it is compared with the effective addresses of all the writes in the Write Buffers Address Data to be written The Effective Address of the LOAD C C C C Write Buffers (FIFO) Writes to the Main Memory Wider Comparators (typically 32 bit) 80
Data Hazards A better response forwarding Also called bypassing Comparators ensure register is read after it is written Instead of stalling until write occurs Use mux to select forwarded value rather than register value Control mux with hazard detection logic 8
Write before Read RF ister file design 2-phase clocks common Write RF on first phase Read RF on second phase Hence, same cycle: Write $ Read $ No bypass needed If read before write or DFF-based, need bypass 82
Control Flow Hazards Control flow instructions branches, jumps, jals, returns Can t fetch until branch outcome known Too late for next IF 83
Control Flow Hazards What to do? Always stall Easy to implement Performs poorly /6 th instructions are branches, each branch takes 3 cycles CPI = + 3 x /6 =.5 (lower bound) 84
Control Flow Hazards Predict branch not taken Send sequential instructions down pipeline Kill instructions later if incorrect Must stop memory accesses and RF writes Including loads (why?) Late flush of instructions on misprediction Complex Global signal (wire delay) 85
Control Flow Hazards Even better but more complex Predict taken Predict both (eager execution) Predict one or the other dynamically Adapt to program branch patterns Lots of chip real estate these days Pentium III, IV, Alpha 2264 Current research topic 86
Control Flow Hazards Another option: delayed branches (later in branch handling techniques!) Always execute following instruction delay slot Put useful instruction there, otherwise nop Losing popularity Just a stopgap (one cycle, one instruction) Superscalar processors (later) Delay slot just gets in the way (special case) 87
Exceptions and Pipelining add $, $2, $3 overflows A surprise branch Earlier instructions flow to completion Kill later instructions Save PC in EPC, set PC to EX handler, etc. 88
Exceptions Even worse: in one cycle I/O interrupt User trap to OS (EX) Illegal instruction (ID) Arithmetic overflow Hardware error Etc. Interrupt priorities must be supported 89
Review Big Picture Datapath Control Data hazards Stalls Forwarding or bypassing Control flow hazards Branch prediction Exceptions 90