College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1
For the rest of the semester, we ll focus o computer architecture: how to assemble the combiatioal ad sequetial compoets we ve studied so far ito a complete computer. Today, we ll start with the datapath, the part of the cetral processig uit (CPU) that does the actual computatios. 2
A overview of CPU desig We ca divide the desig of our CPU ito three parts: The datapath does all of the actual data processig. A istructio set is the programmer s iterface to CPU. A cotrol uit uses the programmer s istructios to tell the datapath what to do. Today we ll look i detail at a processor s datapath. A ALU does computatios, as we ve see before. A limited set of registers serves as fast temporary storage. A larger, but slower, radom-access memory is also available. 3
What s i a CPU? ALU Registers A processor is just oe big sequetial circuit. Some registers are used to store values, which form the state. A ALU performs various operatios o the data stored i the registers. 4
Micro-Ops Trasfer Bus A bus cosists of a set of parallel data lies To trasfer data usig a bus: coect the output of the source register to the bus; coect the iput of the target register to the bus; whe the clock pulse arrives, the trasfer occurs
Bus ad Memory trasfers 6
7 The cotet of register C is placed o the bus, ad the cotet of the bus is loaded ito register A by activatig its load cotrol iput.
Questio A digital computer has a commo bus system for 16 registers of 32 bit each. The bus is costructed with multiplexers. How may selectio iputs are there is each multiplexer? What size of multiplexers is eeded? How may multiplexers are there i the bus? 8
Register files D Moder processors cotai a umber of registers grouped together i a register file. Much like words stored i a RAM, idividual registers are idetified by a address. Here is a block symbol for a 2 k x register file. There are 2 k registers, so register addresses are k bits log. Each register holds a -bit word, so the data iputs ad outputs are bits wide. DA AA k k D data Write D address Register File A address B address A data B data A B k BA 9
Accessig the register file You ca read two registers at oce by supplyig the AA ad BA iputs. The data appears o the A ad B outputs. DA k Write D address D D data You ca write to a register by usig the DA ad D iputs, ad settig = 1. These are registers so there must be a clock sigal, eve though we usually do t show it i diagrams. AA k Register File A address B address A data B data A B k BA We ca read from the register file at ay time. Data is writte oly o the positive edge of the clock. 10
What s iside the register file Here s a 4 x register file. (We ll assume a 2 k x = 4 x register file for all our examples.) decoder DA0 & DA1 Select the register to write i AA0 & AA1 BA0 & BA1 Select the register to read from Mux The -bit 4-to-1 muxes select the two register file outputs A ad B, based o the iputs AA ad BA. Mux 11
Explaiig the register file The 2-to-4 decoder selects oe of the four registers for writig. If = 1, the decoder will be eabled ad oe of the Load sigals will be active. The -bit 4-to-1 muxes select the two register file outputs A ad B, based o the iputs AA ad BA. We eed to be able to read two registers at oce because most arithmetic operatios require two operads. 12
The all-importat ALU The mai job of a cetral processig uit is to process, or to perform computatios...remember the ALU from way back whe? We ll use the followig geeral block symbol for the ALU. A ad B are two -bit umeric iputs. is a m-bit fuctio select code, which picks oe of 2 m fuctios. The -bit result is called F. Several status bits provide more iformatio about the output F: A B V = 1 i case of siged overflow. m C is the carry out. N = 1 if the result is egative. Z = 1 if the result is 0. V C N Z ALU F 13
ALU fuctios For cocrete examples, we ll use the ALU as it s preseted i chapter 4. The fuctio select code is 4 bits log, but there are oly 15 differet fuctios here. We use a alterative otatio for AND ad OR to avoid cofusio with arithmetic operatios. Operatio 0000 F = A 0001 F = A + 1 0010 F = A + B 0011 F = A + B + 1 0100 F = A + B' 0101 F = A + B' + 1 0110 F = A - 1 0111 F = A 1000 F = A B (AND) 1001 F = A B (OR) 1010 F = A B (XOR) 1011 F = A' 1100 F = B 1101 F = sr B (shift right) 1110 F = sl B (shift left) 14
My first datapath Here is the most basic datapath. The ALU s two data iputs come from the register file. The ALU computes a result, which is saved back to the registers. DA 2 D data Write D address Register File AA 2 A address B address 2 BA A data B data, DA, AA, BA ad are cotrol sigals. Their values determie the exact actios take by the datapath which registers are used ad for what operatio. 4 V C N Z A ALU F B 15
A example computatio Let s look at the proper cotrol sigals for the operatio below: R0 R1 + R3 Set AA = 01 ad BA = 11. This causes the cotets of R1 to appear at A data, ad the cotets of R3 to appear at B data. Set the ALU s fuctio select iput = 0010 (A + B). Set DA = 00 ad = 1. O the ext positive clock edge, the ALU result (R1 + R3) will be stored i R0. 1 DA 00 Write D address D data AA A address B address BA 01 11 0010 V C N Z A data Register File A ALU F B data B 16
Two questios D data Four registers is t a lot. What if we eed more storage? Who exactly decides which registers are read ad writte ad which ALU fuctio is executed? DA AA Write D address Register File A address B address A data B data A B BA V C N Z ALU F 17
We ca access RAM also Here s a way to coect RAM ito our existig datapath. To write to RAM, we must give a address ad a data value. These will come from the registers. We coect A data to the memory s ADRS iput, ad B data to the memory s DATA iput. Set MW = 1 to write to the RAM. (It s called MW to distiguish it from the write sigal o the register file.) DA AA D data Write D address Register File A address B address V C N Z A data D0 Q D1 S A ALU F MD B data B BA +5V MW 1 ADRS DATA CS RAM OUT MW = 1 to write to the RAM 18
To read from RAM, A data must supply the address. Set MW = 0 for readig. Readig from RAM The icomig data will be set to the register file for storage. This meas that the register file s D data iput could come from either the ALU output or the RAM. A mux MD selects the source for the register file. Whe MD = 0, the ALU output ca be stored i the register file. Whe MD = 1, the RAM output is set to the register file istead. DA AA D data Write D address Register File A address B address V C N Z A data D0 Q D1 S A ALU F MD Mux B data B BA +5V MW 0 ADRS DATA CS RAM 19 OUT
We ow have a way to copy data betwee our register file ad the RAM. Notice that there s o way for the ALU to directly access the memory RAM cotets must go through the register file first. Here the size of the memory is limited by the size of the registers; with -bit registers, we ca oly use a 2 x RAM. Notes about this setup DA AA D data Write D address Register File A address B address V C N Z A data D0 Q D1 S A ALU F MD B data B BA +5V MW ADRS DATA CS RAM 20 OUT
Memory trasfer otatio I our trasfer laguage, the cotets at radom access memory address X are deoted M[X]. For example: The first word i RAM is M[0]. If register R1 cotais a address, the M[R1] are the cotets of that address. The M[ ] otatio is like a poiter dereferece operatio i C or C++. 21
Example sequece of operatios Here is a simple series of register trasfer istructios: M[R0] M[R0] + 1 = R3 M[R0] R3 R3 + 1 M[R0] R3 This just icremets the cotets at address R0 i RAM. Agai, our ALU oly operates o registers, so the RAM cotets must first be loaded ito a register, ad the saved back to RAM. R0 is the first register i our register file. We ll assume it cotais a valid memory address. How would these istructios execute i our datapath? 22
AA should be set to 00, to read register R0. The value i R0 will be set to the RAM address iput, so M[R0] appears as the RAM output OUT. MD must be 1, so the RAM output goes to the register file. To store somethig ito R3, we ll eed to set DA = 11 ad = 1. MW should be 0, so othig is accidetally chaged i RAM. Here, we did ot use the ALU () or the secod register file output (BA). R3 M[R0] 1 DA 11 AA 00 Write D address D data Register File A address B address V C N Z A data D0 Q D1 S A ALU F MD 1 B data B BA +5V MW 0 ADRS DATA CS RAM MW = 1 to write to the RAM OUT MW = 0 23 to read from the RAM
R3 R3 + 1 AA = 11, so R3 is read from the register file ad set to the ALU s A iput. eeds to be 0001 for the operatio A + 1. The, R3 + 1 appears as the ALU output F. If MD is set to 0, this output will go back to the register file. To write to R3, we eed to make DA = 11 ad = 1. Agai, MW should be 0 so the RAM is t iadvertetly chaged. We did t use BA. 1 DA 11 AA 11 0001 D data Write D address Register File A address B address V C N Z A data D0 Q D1 S A ALU F MD 0 B data B BA +5V MW 0 ADRS DATA CS RAM OUT 24
M[R0] R3 Fially, we wat to store the cotets of R3 ito RAM address R0. Remember the RAM address comes from A data, ad the cotets come from B data. So we have to set AA = 00 ad BA = 11. This seds R0 to ADRS, ad R3 to DATA. MW must be 1 to write to memory. No register updates are eeded, so should be 0, ad MD ad DA are uused. We also did t use the ALU, so was igored. 0 DA AA 00 D data Write D address Register File A address B address V C N Z A data D0 Q D1 S A ALU F MD B data B BA 11 +5V MW 1 ADRS DATA CS RAM 25 OUT
Costat i Oe last refiemet is the additio of a Costat iput. DA AA D data Write D address Register File A address B address BA The modified datapath is show o the right, with oe extra cotrol sigal MB. NOT R0, R1 R0 R1 ADD R3, R3, #1 R3 R3 + 1 SUB R1, R2, #5 R1 R2-5 Costat V C N Z A data A MB ALU F B data S D1 D0 Q B +5V MW RAM ADRS DATA OUT CS D0 Q D1 S MD 26
Summary The datapath is the part of a processor where computatio is doe. The basic compoets are a ALU, a register file ad some RAM. The ALU does all of the computatios, while the register file ad RAM provide storage for the ALU s operads ad results. Various cotrol sigals i the datapath gover its behavior. Next week, we ll see how programmers ca give commads to the processor, ad how those commads are traslated i cotrol sigals for the datapath. 27