Verilog Hardware Description Language HONG@IS.NAIST.JP ROOM: B405
Content Lecture 1: Computer organization and performance evaluation metrics Lecture 2: Processor architecture and memory system Lecture 3: Logic circuit: Combinational circuit and sequential circuit Lecture 4: Number system and Its Importance Lecture 5: Hardware design by HDL Lecture 6: Parallel programming Lecture 7: Hardware design by high-level synthesis Lecture 8: Computer system design and its applications 2
Lecture Information 3
Grading ( 評価 ) Mini-test (40%) Score is based on the number of times that you attend the class and your enthusiastic on doing mini-test. You may get MAX score although your answer is not correct! If you cannot attend the lecture with reasonable reason (ex: attend conference), you can get MAX score if you: Inform about your absent to me via email: hong@is.naist.jp Study from lecture video and submit mini-test by next time. Home-work: (60%) Score is based on the correction of your home-work Bonus (+10%) Your activeness, enthusiastic during the lecture (make question, answer the question, etc.) 4
Overview of Hardware Circuit Design System Block 1 Block 2 Block N Hardware System Verilog HDL Adder Register Memory Comb. Circuit: Do specific function. Adder Mul. Seq. Circuit: Register, memory, etc. Latch Flipflop Digital Circuit Design MUX Comp. Binary Logic gate: Not, And, Or, etc. Comparator Analog Circuit Design Transistors 5
Contents Verilog HDL Sample Designs Quartus II 6
Hardware Description Languages (HDL) Describe the hardware circuit by using codes Code is synthesized into logic gates Require libraries of standard cells Widely used in logic design Verilog HDL and VHDL (Very High Speed Integrated Circuit HDL) Verilog / VHDL Standard cell Libraries Compiler Quartus II netlist Example of netlist 7
Verilog Verilog is one of the two major HDL used in industry and academia Verilog is easier than VHDL Digital systems are highly complex Verilog makes the digital circuit design becomes simple. 4-bit adder 8
Module Basic Unit of Verilog is: MODULE Describes the functionality of the design States the input and output ports module adder_4bit General Definition module module_name ( port_list ); port declarations; variable declaration; description of behavior endmodule Example 9
Numbers Numbers are specified in the form: <size><base format><value> Size: Number of bits that represents the number Base format: b (binary); d (decimal); o (octal); h (hex) Value: value of the number Examples: 4 b0110: 4-bit binary number with value 0110 8 hf7 : 8-bit hexadecimal number with value f7 16 d80: 16-bit decimal number with value 80 10
Quiz What is the meaning of the following numbers? 6 b011000 8 d20 16 h093f 32 d100 9 o725 11
Signal Declaration Internal signals: Net: wire <size> <name> ; Register: reg <size> <name> ; Example: Port signals: Input port: input <size> <name> ; Output port: Net: output <size> <name> ; Register: output reg <size> <name> ; When should a signal be declared as a net / a register? 12
assign versus always (1/2) Assignment : Format: assign <LHS> = <RHS>; Means that whenever any change on the RHS occurs, it will be evaluated and assigned to the LHS. LHS must be a net type signal. Example: 13
assign versus always (2/2) Always blocks Describe events that should happen under certain conditions. The LHS of commands inside always block must be Register type Two kinds of Always blocks always @(posedge clock) begin LHS-1 <= RHS-1 end Type-1: describes the sequential logic (or register). The LHS will change its value at the positive or negative edge of clock signal always @(<signal list>) begin LHS-2 = RHS-2 end What kind of memory that LHS-1 and LHS-2 should be? Type-2: describes the combinational block (or logic gate). The LHS will change its value when one or more signals in the list change the value 14
assign versus always Example (1/3) always assign 15
assign versus always Example (2/3) always assign 16
assign versus always Example (3/3) always assign What is the different between two waveforms? 17
Comments Comment: // : one line comment /* */ : multi-lines comment Note: The language is case sensitive example: a and A are different 18
If else versus case commands These commands can be used inside always blocks only. always @( ) begin if ( <condition> ) begin... end else if ( <condition> ) begin... end else begin... end end Example: if (datain == 2 b00) begin datao <= 2; end else if (datain == 2 b01) begin datao <= 5; end else begin datao <= 10; end 19
If else versus case commands These commands can be used inside always blocks only. always @( ) begin case (<signal name>) <value 1> : command 1; <value 2> : command 2; default: command n; endcase end Example: case (datain) 2 b00: datao <= 2; 2 b01: datao <= 5; default: datao <= 10; endcase 20
Verilog Basic Commands (1/6) assign c = (a < b); If: a=3, b=4 c = 1 a = 5, b = 2 c = 0 21
Verilog Basic Commands (2/6) If: a=5, b=3 amodb = 5 % 3 = 2. If: a = 15, b = 2 amodb = 15 % 2 = 1. 22
Verilog Basic Commands (3/6) Mainly used to present condition inside if command 23
Verilog Basic Commands (4/6) assign command Mainly used to present condition of if command 24
Verilog Basic Commands (5/6) assign b = a << 2; If: a = 10011 b = 1001100 assign b = a >> 2; If: a = 10011 b = 100 assign c = (sel==1)? a : b ; If sel = 1 c = a Otherwise, c = b. Equivalent to MUX gate sel 25 a b 1 0 c
Verilog Basic Commands (6/6) Examples: assign c = a ~ b; assign c = a & b; assign c = a b ; assign c = ~(a & b) ; assign c = ~(a b) ; assign c = a ^ b ; assign c = a ~^ b ; Logic Gates Operator Description ~ NOT & AND OR ~(..&..) NAND ~(....) NOR ^ exclusive or ~^ or ^~ exclusive nor (equivalence) 26
Verilog Sample Designs HONG@IS.NAIST.JP ROOM: B405
Sample design 1 Write Verilog code for below circuits: Wire_1 Y Wire_2 The Generated netlist: 28
Sample design 2 Write Verilog code for below circuits: clk Wire_1 Y Wire_2 29
Sample design 2 - Answer Verilog code Generated netlist 30
Sample design 3 Design a 4-bit counter that has the following waveform: 1 b1 enable + 0 1 clk rst 0 1 0 count 31
Sample design 3 - Answer 32
Sample design 4 Design a counter that has the following waveform: clk 1 How many bits are needed for count signal? rst enable 1 1 Sample_4 3 count 33
Sample design 4 - Answer 34
Quartus II HONG@IS.NAIST.JP ROOM: B405
Quartus II Introduction Quartus II is a software tool provided by Altera. It compiles the Verilog codes into netlist that can be understood by Altera FPGA devices such as: Cyclone, Stratix, etc. Standard cell Libraries Verilog / VHDL Compiler Done by Quartus II Altera Cyclone II FPGA board netlist 36
Summary Lecture 3: Logic circuit: Combinational circuit and sequential circuit Lecture 4: Number system and Its Importance Lecture 5: Hardware design by HDL 37
Basic Logic Circuits Basic Logic Gates: Not, And, Or, Xor, Xnor, etc. Combinational Circuits Arithmetic Operator: adder, multiplier, etc. Encoder Multiplexer Comparators Sequential Circuits Memory Elements: Latch, FlipFlop, Register, etc. Sequential Circuits 38
Number Systems Number System Introduction Number systems used by human Number systems used by computer: binary, decimal, octal, hexa-decimal Number System Conversion Signed Number Representation Sign-magnitude One s complement Two s complement Fractional Number Representation Fixed point number Floating point number Size of Number: Complexity vs. Performance 39
Verilog HDL Verilog HDL Module Always v.s. Assign If else command Case command Verilog Basic commands Sample Designs Quartus II 40
Next Class 先進情報科学特別講義 Ⅱ,Ⅳ (130047, 130049) Advanced Cutting-edge Research Seminar Ⅱ&Ⅳ (130047, 130049) Time: 12 月 1, 6, 8, 13 日 9:20--10:50 Course Name: Research Trends on High Throughput Wireless Communication Systems ( 高スループット無線通信システムに関する研究動向 ) Place: L1 room 41
Course s Content Overview the MAC & PHY layers Advanced techniques on MAC & PHY to improve data rate PHY MAC Wireless com. transceiver 42