ECE 601 - Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers Fall 2001 Final Version (Important changes from original posted Exercise 1 shown in color) Variables In Verilog, what are nets used for? A: For structural connectivity What are registers used for in Verilog? A: As an abstraction of storage (May or may not be real physical storage) What is the generic name for both nets and registers? A: Signals What is a single bit net called? A: A scalar net What is a multiple bit register called? A: A vector register Logic Values Give the four basic Verilog signal values and their meanings A: 0 - Logical 0 or FALSE A: 1 - Logical 1 or TRUE A: x, X - Unknown logic value A: z, Z - High impedance condition Give the number of driving strengths used for switch level modeling of MOS devices in Verilog: A: 4 each for 0 and 1 net values and 2 for HiZ values for a total of 10. Give the number of charge strengths used for switch level modeling of MOS devices in Verilog: A: 3 each for 0 and 1 net values for a total of 6. Thus there are 16 total strength values. Data Type - Nets Give the two methods for explicitly assigning a value to a net. A: Continuous assignment A: force release procedural continuous assignment Give the two methods for implicitly assigning a value to a net. A: By being connected to an output terminal of a primitive A: By being connected to an output port of a module Net Semantics Give the meaning of each of the following net types; indicate whether there can be just a single driver or multiple drivers. wire A: Single driver, connectivity only; no logical 1
tri A: Multiple drivers, same as wire, but 3-stated in hardware wand A: Multiple drivers - wired and wor A: Multiple drivers - wired or triand A: Multiple drivers, same as wand, but 3-state in hardware trior A: Multiple drivers, same as wor but 3-state in hardware supply 0 A: Global net for GND supply 1 A: Global Net for VCC (VDD) Net Declaration Syntax Explain the difference between a net declared as vectored and a net declared as scalared. A: vectored Multiple-bit net treated as a single object - cannot reference individual bits or part-select A: scalared - Bits can be referenced individually and as parts What is the default for a net, vectored or scalared? A: scalared Net Examples - Single Driver Describe fully the net(s) declared by each of the following net declarations. wire x; A: 1-bit wire x; wire x, y; A: 1-bit wires x and y. wire [15:0] data, address; A: 16-bit wires data and address with MSB 15 and LSB 0. wire vectored [0:7] control; A: 8-bit wire control with MSB 0 and LSB 7 that can be instantiated only as all 8 bits. data[15] (instantiation) A: Use of bit 15 of data address[15:8] (instantiation) A: Use of bits 15 down through 8 of address wire [15:0] address = offset + index; A: Declaration of 16-bit wire address with MSB 15 and LSB 0 and continuous assignment = offset + index Net Examples - Multiple Drivers 2
Describe in detail the net(s) declared by each of the following net declarations. wor interrupt_1, interrupt_2; A: Two 1-bit wired or nets called interrupt_1 and interrupt_2 tri [31:0] data_bus, operand_bus; A: Two 32-bit three-state nets called data_bus and operand_bus with MSB 31 and LSB 0 supply0 [31:0] GND; A: 32-bit GND net with MSB 31 and LSB 0 supply1 [23:0] VDD; A: 24-bit VDD net with MSB 23 and LSB 0 Initial Value & Undeclared Nets What is the default initial value of a net at t sim = 0? A: The initial value is x. What is the default type for a net that is not declared? A: Defaults to type wire How can the default type for a net that is not declared be changed? A: By a default_nettype compiler directive Data Type Register Register Semantics Give the function that each of the following register types performs. reg A: Stores a logic value integer A: Supports computation time A: Stores time 64-bit unsigned real A: Stores values as real numbers realtime A: Stores time values as real numbers Register Assignment List four Verilog constructs within which a register can be assigned. A: a procedural statement A: a user-defined sequential primitive A: a task, or A: a function. List two Verilog constructs by which a register can never be assigned. A: a primitive gate output or A: a continuous assignment 3
Register Examples Describe the register(s) declared by each of the following register declarations; give the number of bits in all cases. reg a, b, c; A: Three 1- bit register: a, b, and c reg [15:0] counter, shift_reg; A: Two 16-bit registers with MSB 15 down to LSB 0: counter and shift integer sum, difference; A: Two integer registers named sum and difference of length wordlength of machine, but at least 32 bits Strings What is the data type for a string? A: A string has no explicit data type A string must be stored in reg (or array). Describe a register with identifier buffer for storing a string of 32 8-bit characters. A: reg [255:0] buffer; Constants Declaration of parameters A sequential circuit has three states A, B, and C with state codes 00, 01, and 10, respectively. Write a parameter statement assigning these codes to their respective states. A: parameter A = 2 b00, B = 2 b01, C = 2 b10; The following gives a parameter regsize and its instantiation. If n = 8, how many bits are in reg R and how are they numbered? parameter regsize = n; reg R[0: n - 1]; A: 8-bit register with MSB 0 and LSB 7. Operators 4
Give the function that each of the operators listed performs: Arithmetic (binary) + A: addition (2 s complement modulo 2 n ) - A: subtraction (2 s complement modulo 2 n ) * A: multiplication / A: division % A: modulus (remainder of first operand divided by second operand) Arithmetic (unary) + A: positive sign (if x or z in operand, result is all x) - A: negative sign (if x or z in operand, result is all x) Bitwise ~ A: bitwise not & A: bitwise and A: bitwise or ^ A: bitwise exclusive or ~^ or ^~ A: bitwise exclusive nor Reduction & A: and of all bits in operand ~& A: nand of all bits in operand A: or of all bits in operand ~ A: nor of all bits in operand ^ A: exclusive or of all bits in operand ~^ or ^~ A: exclusive nor of all bits in operand Logical! A: Logical not && A: Logical and A: Logical or = = A: Logical equality (A = B with result unknown if x or z present)!= A: Logical inequality (A not = B with result unknown if x or z present) = = = A: Case equality I( A = B with exact match including x and z values)! = = A: Case inequality (A not = B with any mismatch including x and z values) Relational < A: Less than >= A: Greater than or equal to > A: Greater than <= A: Less than or equal to Shift >> A: Right shift with 0 fill (of left operand shifted by the number of bits given by the right operand) 5
<< A: Left shift with 0 fill (of left operand shifted by the number of bits given by the right operand) Conditional? : A: (If operand 1, then operand 2, else operand 3) Concatenation and Replications {,} A: Concatenate operands given {int{ }}A: Form vector which is replication of operand int times Expression Bit Widths Depends on: widths of operands and types of operators Verilog fills in smaller-width operands by using zero extension. Final or intermediate result width may increase expression width Width (Unsized constant number) = same as integer (usually 32) Width (Sized constant number) = number of bits specified. Arithmetic binary and bitwise x op y where op is +, -, *, /, %, &,, ^, ^~: Bit width = max (width(x), width(y)) What is the width of A + B for reg[7:0] A; reg[15:0] B;? A: 16 Will the assignment statement assign result = (A+B) >> 1; work properly for all possible pairs of 16-bit operands for reg[15:0] A, B;? A: No, lose overflow Arithmetic unary op x where op is +, - Bit width = width(x) Bitwise negation op x where op is ~ Bit width = width(x) Logical, relational and reduction x op y where op is = =,!=, = = =,!= =, &&,, >, >=, <, <= or op y where op is!, &,, ^, ~&, ~, ~^ Bit width = 1 What is the bit width of (X && (A + B)) for wire X; wire [7:0] A, B;? A: 1 Shift x op y where op is <<, >> Bit width = width(x) Conditional x? y : z 6
Bit width = max(width(y), width(z)) What is the bit width of assign result = X? A:B; for wire X; reg[9:0] A; reg[18:10] B; A: 10 Concatenation {x,, y} Bit width = width(x) + + width(y) What is the bit width of {A, B, C} for wire A; reg[7:0] B; reg [15:0] C;? A: 25 Replication {x{y,, z}} Bit width = x * (width(y) + + width(z)) Expressions with Operands Containing x or z Arithmetic If any bit is x or z, result is all x s. Divide by 0 produces all x s. What is the result of assign result = A + B; for A = 4'b1100; B = 2'b11? A: 1111 What is the result of assign result = A + B; for A = 4'b1100; B = 4'bx11? A: xxxx Relational If any bit is x or z, result is x. Logical = = and!= If any bit is x or z, result is x. If lengths of operands are unequal, 0-fill shortest one on left. = = = and!= = All bits including x and z values must match for equality; otherwise unequal. If lengths of operands are unequal, 0-fill shortest one on left. What is the value of (4'b0011) = = (2'b11)? A: 1 Can (4'b0011) = = = (2'b11)? be evaluated? Explain your answer. A: Yes. 0-fill is used as well here; operands as given do not need to be equal length. &&, combines logical values 0,1, x. Multiple bit operands map to single bit as follows: If contains a 1 anywhere, maps to 1. If all 0 s, maps to 0. Otherwise, maps to x. Bitwise Defined by tables for 0, 1, x, z operands. Reduction Defined by tables as for bitwise operators. Shifts z changed to x. Vacated positions zero filled. 7
Conditional If conditional expression is ambiguous (e.g., x or z), both expressions are evaluated and bitwise combined as follows: f(1,1) = 1, f(0,0) = 0, otherwise x. What is the value of result in assign result = (2'b1x)? 4'b0011: 4'b0101; A: Since 2'b1x contains a 1, it is known to be non-zero, so is mapped to a 1 (true) giving result = 4'b0011. Suppose that 1'bx replaces 2'b1x. 1'bx maps to x, giving, by the rules shown, result = 4'b0xx1. The rules given correspond to the behavior of a multiplexer implementing the conditional (If both data values are equal to 1, the output is 1 regardless of the select value. Likewise, for both data values equal to 0. If the data values are opposite, then the output is unknown for an unknown value on the select input. 8