Standard Cell Based Design Flow Using Modelsim, Buildgates, and Silicon Ensemble

Arifur Rahman, Spring 2004, Polytechnic University, NY Standard Cell Based Design Flow Using Modelsim, Buildgates, and Silicon Ensemble Mapped Netlist Back Annotation using SDF File and mapped netlist RTL Based Design (Verilog/VHDL) Verification in Modelsim Synthesis in Buildgates Required Library Files: Alf file (IBM_CU11_SC.adb and IBM_CU11_IO.adb) Lef file (ibm_6ml_sc.lef) for physical synthesis. IBM_CU11_SC.sym file in user s home directory Timing Verification. Area, power, and performance optimization. Generation of DEF file for (placement and) routing in SE or PKS_Shell. Generation of mapped netlist for post-synthesis verification. Generation of SDF file for back annotation Placement and Routing in Silicon Ensemble or PKS_Shell Required Library Files: *lef file, *def file, etc. Timing constraint file for timing driven P&R, mapped HDL file for P&R from HDL GDSII

Documentation on Buildgates and Silicon Ensemble [The purpose of this document is to help you get started with logic synthesis using standard cells and perform post synthesis verification, timing verification, placement, and routing. It is assumed that you are familiar with RTL-level verification using Modelsim] Some example files for standard cell based synthesis are provided in /opt/cadence/local/el644/ibm_library/ directory. p_adder.v contains RTL-level description of the adder we would like to synthesize. ibm_5lm_sc.lef is the 5-metal layer physical design library associated with the standard cells, and *tcl is the script file for synthesis in pks_shell. For logic synthesis, we can use either physically-driven (pks_shell) or non physically-driven (bgx_shell) synthesis. Some of the commands used in the *tcl file (such as read_lef,,, etc.) are suitable for pks_shell only and should be commented out for bgx_shell based synthesis. Generally, before you try to synthesize your RTL code (vhdl/verilog) in Buildgates (pks_shell or bgx_shell), it is assumed that your design has been verified in Modelsim. Let's assume we have verified our design, p_adder.v, and we would like to synthesize it. First, we perform synthesis using Buildgate Extreme, bgx_shell, without providing any information about the design's physical placement. During synthesis, we will generate a mapped netlist using do_optimize command (included in the *tcl file). The mapped netlist will consist of specific logic cells that are available in the library, IBM_CU11, which has been specified in the *tcl file. This mapped netlist needs to be verified in Modelsim for correct functionality. Conventional approach to pre- and post-synthesis verification can be summarized in the following block diagram: Input Test Vectors Pre-Synthesis RTL Code Post-Synthesis RTL Code Comparison of Expected Output Different Outputs. Debugging of RTL code and re-synthesis Identical Outputs. Verification is complete In addition of correct functionality of the mapped netlist, we need to make sure setup and hold time requirements are met for specific clock frequency. If timing violation persists, optimization at algorithmic and synthesis level can be performed. After we are confident that our design is functionally correct, we can perform a physically-driven synthesis using pks_shell, followed by routing. We could have performed physically driven synthesis (using pks_shell) to begin with instead of non-physically driven synthesis (using bgx_shell). However, it (physically driven synthesis) takes relatively long time and if our initial design is not functionally correct or requires optimization, there is inefficient use of design time and resources. In sub-micron technologies, where interconnect delay is significant, pks_shell based synthesis provides placement information during synthesis. As a result, the assumptions on wiring delays are more accurate compared to non-physically driven synthesis. So, it is recommended that bgx_shell based synthesis be followed by pks_shell based synthesis for timing accuracy and to generate a placed netlist (*.def file). If you don t meet timing constraints, you can perform optimization at algorithm, synthesis, and physical design levels. Please, consult the BG user manual for detailed descriptions on such techniques. Once you have completed physically driven synthesis in BG, you can generate an SDF file (using the command write_sdf in Buildgates), which will capture parasitic RC parameters associated with interconnects. The SDF file can be read into Modelsim for back annotation. Using back-annotated netlist, you can capture logic and interconnect delays, glitches, etc. associated with your design in Modelsim.

Before you generate an SDF file from BG (pks_shell), make sure to dissolve all hierarchies in your synthesized netlist. Also, make sure the mapped design, which is used to generate the SDF file is identical to the one being read in Modelsim. In this course, we will perform placement and routing in Silicon Ensemble. At the end of physically driven synthesis in pks_shell, make sure to create a *.def file, using write_def, for your placed design. In SE, the physical design aspects of the library file (*.lef) is read, followed by the physical design file (*.def). Def file contains information about the placement of cells and I/O terminals. In SE, we can define the VDD/VSS distribution wires and make changes to the *.def file if necessary. These steps are followed by the routing process. If you don t want to use SE, routing can also be performed in BG. After routing, you can generate parasitic RC files from BG/SE that can be read in Modelsim to create back-annotated netlsit. To view the metal layers correctly in SE, you need to initialize their settings. In /opt/cadence/local/el644/ibm_library/ directory, there is a file called sample.mac. Execute this file from SE, and it will set the layer colors correctly. You can save your final layout as an *.hpgl file so that it can be read during another session in SE. There are several freely available software tools that can be downloaded from the web to convert *.hpgl to *.pdf or other formats in case you like to incorporate your in *.ppt slide or a report. The Modelsim tutorial is available in /eeweb.poly.edu/cad/. This year, instead of vtlib, we will be using IBM's library. Please read the relevant tutorials on BG and SE available on /opt/cadence/local/el644/synthesis/ (BG51) and (SE) to learn more about synthesis, placement, routing, HDL modeling, low-power synthesis, clock tree generation, etc. Here are some useful commands for BG and SE Buildgates bgx_shell -gui & [invokes BG Extreme] pks_shell -gui & [invokes BG PKS] While in bgx_shell or pks_shell, source <filename.tcl> executes all the commands in filename.tcl. Read the p_adder.tcl file to become familiar with commonly used commands for logic synthesis in BG Synthesis do_optimize command, invoked from BG design environment, does the following: unification, constant propagation, structuring, redundancy removal, resizing, buffering, cloning, area reclaim, fixing design rule violation, resource sharing, scan connection, power sleep-mode option, etc. To speed up the synthesis process, one can stop after the mapping using do_optimize -stop_after_mapping... this way, some of the optimization steps will be skipped. If you have a large design, first, you may want to do a simple mapping,

followed by functional verification. Then you perform incremental optimization. To optimize a group of objects/path one can use set_path_group command To view timing report on path groups, use report_path_group_timing Definitions of Multiple Clocks set_path_group -name 200MHz -to_clock slow_clk1 set_path_group -name 400MHz -to_clock slow_clk2 Optimization With Desired Margin: Using -target_slack one can specify which slack values should be critical. A negative value can be specified to make the tool stop early, a positive value makes the tool optimize even beyond zero slack Power Optimization In order to perform power optimization, you need to make sure appropriate power models for dynamic and leakage power are included in your standard cell library. Our standard cell library is in *lib format, which is the preferred format for synthesis tools available from Synopsys. In older versions of BG, *lib had to be converted to a different format such as *.adb or *.alf to be readable by BG. However, in newer versions of BG, *.lib files can be read directly using the following commands: read_dotlib <file_core> where <file_core> is /opt/ibm_cu11/v11.0/synthesis/synopsys/ibm_cu11_sc.lib for IBM s standard cell library read_dotlib <file_io> where <file_io> is /opt/ibm_cu11/v11.0/synthesis/synopsys/ibm_cu11_io.lib for IBM s I/O library Buildgates can perform various types of optimization for low-power using clock gating, gate-level optimization, sleep mode operation, etc. Please consult the low-power PKS synthesis guide for more information. To estimate power dissipation or to quantify the savings in power dissipation associated with low-power design techniques, it is important to estimate power dissipation accurately. If there is no activity information, 50% activity factor at the input terminals is assumed and the resulting calculation of dynamic power dissipation may not be very accurate. To model activity factor accurately, an activity file (*.vcd) can be created in Modelsim for a set of input test vectors. To estimate power dissipation of a synthesized netlist, make sure the identical (synthesized) netlist has been used in Modelsim to generate the activity file. Once the activity file has been generated, it should be read in BG, followed by estimation of power dissipation. A method for creating *.vcd file is presented at the end of this document.

do_optimize -clock_gate [useful for clock gating] do_xform_optimzie_power [synthesis for low power] Hold Time Violation Set PVT conditions using set_global_pvt_early_path min. i.e. minimum path delay will be considered. Now use do_xform_fix_hold do_xform_fix_hold -minimize to fix hold time violation with minimal impact on setup time violation Fixing Timing Violation To report 1000 failing timing paths in a design, use report_timing -net -max_points 1000 -max_slack 0 After figuring out the root cause of timing failure, physical placement of cells may have to be changed. Restructuring of failing paths can be done using do_optimize For Area Reclaim use do_xform_reclaim_area -resize After back annotation of RC values, if timing violation persists, and if you don't want to do any major optimization procedure or reclaim area, you can resize the buffers in critical nets without reclaiming area using do_optimize -ipo Reading extracted RC files read_sdf read_spf or read_spef Silicon Ensemble seultra m=<memory size> & [invokes SE] -m option can be skipped if you want to use the default memory size. For a large design, you may have to increase the memory size. Use seultra help for relevant options. SE can be run in graphical or batch mode. You can also create a *mac file with a list of SE based commands and execute them in batch mode or from SE s GUI. When you run SE, it creates a journal file (*.jnl) that lists all the commands being executed. A simple way is to create a *mac file is to edit your *.jnl file to get rid of unnecessary commands and save it as a *.mac file. If you run SE related commands from the pull down menu, in the lower part of you GUI, you will also find the ASCI version of these commands.

Methods for Creating Value Change Dump (VCD) file for estimating power consumption (Kaijie Wu) To create a VCD file, you need to do the following: Synthesize your VHDL code to a mapped netlist using Buildgates o After you run do_optimize in BG (pks_shell), use write_vhdl -hier work_dir/mapped.vhd o Usually, BG will keep the entity name unchanged, e.g. the same as your original VHDL code, and name the new architecture as netlist o After you simulate both original VHDL code and the synthesized (i.e. mapped) code using ModelSim, you will have two architectures under your top entity name in ModelSim s library view, as shown in following screenshot. A VCD file is generated based on simulating the netlist architecture. If you are not sure how to select netlist architecture, you can delete the other architecture by selecting it in ModelSim and pressing delete button Make sure the entity name of your VHDL netlist is in lower case. The ModelSim simulator is case sensitive Prepare a testbench file of your top entity or provide a do file that specifies the values for inputs Figure 1. Screenshot of Modelsim s graphical interface Here is a *.tcl file for simulation and generation of the *.vcd file.

vsim work.your_top_entity vcd file give_a_name.vcd # here you create an empty *.vcd file vcd add / your_top_entity/* view wave add wave -r /* run 1000ns quit f # finish recording and close the *.vcd file Now a give_a_name.vcd file is created. It is a text file and you can open it to see its content. Usually, an easy way to figure out if you have a correct file is to check if all signals in your netlist architecture, not only the signal you defined but also the signals created by the synthesis tool such as BG, are recorded in the VCD file. In the following example of a VCD file, the inputs and outputs, named by you, are included. It also includes some other node names, which are generated by the synthesis tool. Example of a VCD File $date Wed Apr 14 20:23:39 2004 $end $version ModelSim Version 5.7a $end $timescale 1ns $end $scope module tb_des_enc $end $scope module dut $end $var wire 1! rst $end $var wire 1 " clk $end $var wire 1 # enc_input [63] $end $var wire 1 $ enc_input [62] $end $var wire 1 % enc_input [61] $end $var wire 1 & enc_input [60] $end $var wire 1 ' enc_input [59] $end $var wire 1 ( enc_input [58] $end $var wire 1 ) enc_input [57] $end $var wire 1 E! n_3083 $end $var wire 1 F! n_3080 $end $var wire 1 G! n_2872 $end $var wire 1 H! n_2870 $end $var wire 1 I! n_2868 $end $var wire 1 J! n_2866 $end $var wire 1 K! n_2864 $end $var wire 1 L! n_2862 $end $var wire 1 M! n_2860 $end $var wire 1 N! n_2859 $end $var wire 1 O! n_2855 $end $var wire 1 P! n_2854 $end

$var wire 1 Q! n_2851 $end $var wire 1 R! n_2847 $end $var wire 1 S! n_2845 $end $var wire 1 T! n_2843 $end $var wire 1 U! n_2841 $end $var wire 1 V! n_2839 $end Once the VCD file is generated, switch back to BG (pks_shell or bgx_shell) and run the following command: lpsvcd2tcf.exe <your_top_entity_name> <your_vcd_file_name> output_file <your_tcf_file_name> When you run this command in BG, make sure to comply with the following guideline to define <your_top_entity_name>: First, top entity of your netlist should be set as the top module If you use a do file to provide the stimulus in Modelisim, your <your_top_entity_name> is probably the same as the top module name However, if you use a test bench to generate the stimulus and you instantiate your design as a component called dut within your test bench [ dut: top_entity_name port map (x, y, z, )] <your_top_entity_name> should be the instance name dut instead of your top entity name. I have created a test bench, tb_des_enc, and the instance name of my design is dut (usually, indicating design under test), as shown in the bold line of the VCD file. So, I need to use dut as my <your_top_entity_name> in BG, instead of tb_des_enc