butrer that the ~ simlply 8 triin а single in Figш'е has а (а) In~uI Tгi-slale conlгol (active high) (Ь) l L~ Н Read lalch -, ТВ2 Vcc Inleгnal --4~-Гi)-()l CPU bus О Q Р1,Х Wгile (О latch -f---i Clk Q \-------1 Load (LI) г---.,.-- РI, Х pin (с) H~ v I н (d) Figure С-9, Tri-State BlIffer High-impedence ( open-ciгcuil) the OlltPllt of 74LS245 and 74LS244 сап sink and of current than othel' LS gates, See ТаЫе С-4, That [ог driver when а signal is tгavelling а long disto drive тапу inpllts, lan.-otll, пех! we discllss the structure of 8051 Рl - Р3 since theil' structuгe is slightly dif- Read pin ----1 ТВI Figllre С-10. 8051 Port 1 Strllctllre Also notice that in Figure С-] О, the 8051 p0l1s have both the latch and buffer, Now the question is, in reading the port, ш'е we reading the status of the input pin ог аге we reading the status of the latch? That is ап extremely important question and its answer depends оп which instruction we аге using, Therefore, when reading the P0l1S (Ьеге аге two possibilities: О) reading (Ье input pin, ог (2) reading the latch, ТЬе аьоуе distinction is уегу impol1ant and must Ье understood lest уои damage the 8051 port, Each is dеsсгiьеd next, Reading the input pin As we stated in Chapter 4, 10 make апу bits of апу port of 8051 ап input port, we fil'st must '>Jl'ite а 1 (Iogic high) (о that bit, Look а! the following sequences of events to see why, ], As сап Ье seen [гот Figure С-]], Ьу writing 1 to the рог! Ы! it is written to the latch and the D latch has "high" оп its Q, Therefol'e, Q = ] and Q = О, 2, Since Q = о and is connected (о the transistor М] gate, the М 1 transistol' is off, 3, When the М] transistol' is off, it blocks апу path to the g1'ound [ог апу signal connected to the input pin and the input signal is directed to the tri-state ТВ], 4, When геаdiпg the input port in instructions such as "MOV А, Рl " we аге real 'у reading the data ргеsепt а! the pin, 'П othel' wol'ds, it is bringing into the CPU the status of the external pin, This instruction activates the read pin of ТВ I (tristate buffel' ]) and lets data а! the pins flow into the CPU's internal bus, Figures C-II and С-] 2 show high and low signals а! the input, l'espectively, bldlirel~tig,nal they а" have Ihe following Read lalch ----, ТВ2 Vcc Load (L 1) and its three components, The other with extra circuitry to allow their С-I0 that the LI load is ап interend ofthis section, that is по! the High Inleгnal --4---.jГi)-()l '1' РIХ CPU bus О Q pin РI'Х 'О ' Wгile 10 lalch -f---; Clk Q 1------; МI :v Off Read pin ----1 ТВI Figure С-Н. Reading "Нigh" at InplIt Pin APPENDIX С: IC TECHNOLOGY AND SYSTEM DESIGN ISSUES 385

Read lateh -, Inteгnal CPU bus - ТВ 2 '" "4--Jo-()! Wгite (о lateh -f--~ О Q - '1 ' Р1,Х /1 1" ТВ1 Read pin -----1 ' О ' Уее Clk Q М1 Figure С -12. Reading "Lo\v" а! the IlIp\lt Pill Writing "О" to the port Off I I Load (L 1) Low ~ Р1,Х The аьоуе discussion showed why we must write а "high" to the ports bits in order to make them аll input роп, What happens if we write а "О" (о а pol1 that was сопfigurеd as ап input pol1? F!'Om Figure C- 13 we see that if we wl'ite а О (low) (о рог! bits, then Q = О and Q = 1, As а l'esult ofq = 1, the М 1 transistol' is "оп", lf МI is "оп," it p!'ovides the path (о ground for both LI and the input pin, Therefol'e, апу attempt to read the input pin wi ll always get the " Iow" ground sigпаl regardless of the statlls of the input pin, TIlis сап also lead (о damage to the pol1, as explained next. pin Read lateh, ТВ2 Усе Internal -4--JГO-()! CPU bus О Q ' О' '1 ' pin Р1,Х Wгite (о lateh -Е--" Clk Q f-------i ~M1 Оп Read pin... ТВ1 will damage М1 Figllre С -13. Never Со пп ес! Direct V се to the 8051 POl't Pin Avoid damaging the port When connecting а switch (о ап inpllt pol1 of the 8051 we must Ье vel'y careful, This is dlle to the fact that the wrong kind of соппесtiоп сап damage the port, Look а! Figure C-lЗ. Ifa switch with У ее and ground is connected directly to the pin and the М 1 transistor is "оп" it will sink СUl'l'еп! f!'om both internal load L 1 and external V сс ' This сап Ье (оо much СUl'l'еп! [ог М 1 and will blow the (гап sistor and, as а l'eslllt, damage the POl't bit, Thel'e аге several ways (о avoid thi s ргоыет, They ш'е shown in Figures C-14, C- 15, and C-16, 386

Port 1 Ршt 1 occupies а total of 8 pins (pins 1 through 8). lt сап Ье used as input ог output. In contrast to port О, this port does not need апу pull-up resistors since it already has pull-up ге s i stшs internally. Upon reset, port 1 is сопfigшеd as ап output port. For example, the following code will continuously send ои! to poli J the alternating values 55Н and ААН. MOV А, #55Н ВАСК : MOV Р l,а ACALL DELAY CPL А SJMP ВАСК 88

Port О as input Vcc Port 1 as input With resistol"s connected (о port О, in order to make it ап input, РО.О the РOl"! must Ье programmed PO.11----'~+_+ +_+_j-+_ "u Ьу writing 1 to О55000 8751 ~~:~ l аll the bits. 'П the following code, port О is соп PO.5f-------J.._j-+_ 8951 РО.4 о PO.6f---------"-t- figured first as ап input PO.7f---------'- poli Ьу writing 1 s (о it, and then data is l'eceived fюm that port and sent (о ~.-:-=----: --:: -' Р 1. Figllre 4-4. Рог! О with PIlII-Uр Resistors MOV A, #OFFH ; А = FF hex MOV РО, А ;make РО ап i np u t port ; Ьу writ ing all 15 to it БАСК : MOV А, РО ; get data from РО MOV Р1, А ; 5end it to port 1 ;keep doing it SJMP БАСК То make port 1 ап input port, it must programmed as such Ьу writing 1 (о аll its ~its. The reason for this is discussed in Appendix С.2. 'П the following code, port 1 IS configured first as ап input poli Ьу writing 1 s (о it, then data is received fюm that port and saved in R7, R6, and R5. MOV A, #OFFH ; A=FF hex MOV Р1, А ;ma ke Р1 an input port ;Ь у writing all 15 to it MOV А, Р1 ; get data from Р1 MOV R7,A ; save it in reg R7 ACALL DEALY ;wait MOV А, Р1 ; get another data from Р1 MOV Rб, А i save i t in reg Rб ACALL DELAY : wa i t MOV А,Р1 ; get a nother data from Р1 MOV R5, A isave it in reg R5 Dual role of port О As shown in Figше 4-1, POlt О is also designated as ADO - AD7, allowing it (о Ье used for both address and data. When connecting ап 8051 /31 (о ап exterпаl memory, port О provides both address and data. The 8051 multiplexes address and data through port О (о save pins. ALE indicates if РО has address or data. When ALE = О, it provides data ОО - D7, but when ALE = 1 it has address АО - А 7. Therefore, ALE is used for demuliplexing address and data with the help of а 74LS373 latch, as we will see in Chapter ]4. Port 1 РOI"! 1 occupies а total of 8 pins (pins 1 through 8). It сап Ье used as input or output. 'П contrast (о poli О, this port does по! need апу pull-up resistors since it already has pull-up resistol's internally. Upon reset, РOl"! ] is сопfigшеd as ап output port. For example, the following code will continuously send out to port 1 the alternating values 55Н and ААН. БАСК: MOV А, #55Н MOV Р1, А ACALL DELAY CPL А SJMP БАСК 88