ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 5, 8 Memory: Periphery circuits Today! Memory " RAM Memory " Architecture " Memory core " SRAM " DRAM " Periphery " Serial Access Memories Penn ESE 57 Spring 8 - Khanna Memory Overview Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH L-K Bit Line Storage Cell A K A K+ A L- Row Decoder Word Line Sense Amplifiers / Drivers M. K Amplify swing to rail-to-rail amplitude A A K- Column Decoder s appropriate word - (M bits) Penn ESE 57 Spring 8 - Khanna Read-Write Memories (RAM)! Static (SRAM) " Data stored as long as supply is applied " Large (6 transistors/cell) " Fast " Differential! Dynamic (DRAM) " Periodic refresh required " Small (-3 transistors/cell) " Slower " Single ended 6T SRAM Cell! Cell size accounts for most of memory array size! 6T SRAM Cell " Used in most commercial chips " Data stored in cross-coupled inverters! Read: " Precharge BL, BL BL bit " Raise WL word WL! Write: " Drive data onto BL, BL " Raise WL bit_b BL Penn ESE 57 Spring 8 - Khanna 6
6-transistor CMOS SRAM Cell CMOS SRAM Analysis (Read) VDD WL BL M5 Q = M4 Q = M6 BL VDD V M VDD C bit C bit Penn ESE 57 Spring 8 - Khanna W k n,m L ( V DD ΔV V Tn ) = = k n,m 5 W (V L DD V Tn )ΔV ΔV Penn ESE 57 Spring 8 - Khanna 5 ΔV =V Tn W L ( V DD V Tn ) = W (V DD.5V Tn )V Tn L 5 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Write) VDD WL Voltage Rise (V)..8.6.4. Q = M5 BL VDD = M M4 Q = M6 BL = PR = W 4 L 4 W 6 L 6.5..5 Cell Ratio (CR).5 3 k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V Q V Q V Q =V Tn k n,m 4 k n,m 6 = ( V Tn ) ( V Tp )V Tn V Tn Penn ESE 57 Spring 8 - Khanna CMOS SRAM Analysis (Write) Consider (5T SRAM) PR = W 4 L 4 W 6 L 6! How should we size the devices for read and write without faults? Penn ESE 37 Fall 8 - Khanna
Pre-Charge V dd / Reference DRAM! Use one phase of clock to charge a node to some initial value before operation! Smaller than SRAM! Require data refresh to compensate for leakage Penn ESE 37 Fall 8 - Khanna 3 4 3-Transistor DRAM Cell -Transistor DRAM Cell WWL BL BL WWL WL BL WL Write "" Read "" RWL RWL M C S X GND V T X M3 M M C S X BL BL VDD-VT VDD-VT No constraints on device ratios Reads are non-destructive Value stored at node X when writing a = V WWL-V Tn ΔV CBL BL VDD/ C ΔV V BL V ( PRE V BIT V ) S = = ----------------------- PRE C S + C BL sensing VDD/ Write: CS is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance Voltage swing is small; typically around 5 mv. DRAM Cell Observations! T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out! DRAM memory cells are single ended in contrast to SRAM cells! The read-out of the T DRAM cell is destructive " Read and refresh operations are necessary for correct operation! Unlike 3T cell, T cell requires presence of an extra capacitance that must be explicitly included in the design! When writing a into a DRAM cell, a threshold voltage is lost " This charge loss can be circumvented by bootstrapping the word lines to a higher value than Memory Periphery 3
Array Architecture Array Architecture! n words of m bits each! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! Good regularity easy to design! Very high density if good cells are used 9 Array Architecture Array Architecture! n words of m bits each! n words of m bits each! Good regularity easy to design! Very high density if good cells are used! Good regularity easy to design! Very high density if good cells are used Decoders Decoders! n: n decoder consists of n n-input AND gates " One output needed for each row of memory " Build AND from NAND or NOR gates Static CMOS A word 8 word word A 4 word word3 4 4
Large Decoders! For n > 4, NAND gates become slow " Break large gates into multiple smaller gates A3 A A word Predecoding! Many of these gates are redundant " Factor out common A3 gates into predecoder A " Saves area " Same path effort A predecoders word word of 4 hot predecoded lines word word word3 word word3 word5 word5 5 6 Row : Precharge NAND Row : Precharge NOR 7 8 Array Architecture Column Circuitry & Bit-line Conditioning! n words of m bits each! Good regularity easy to design! Very high density if good cells are used 3 5
Column Circuitry Bitline Conditioning! Some circuitry is required for each column " Bitline conditioning " Precharging " Driving input data to bitline " Sense amplifiers " Column multiplexing (AKA Column Decoders)! Precharge bitlines high before reads φ BL bit bit_b BL 3 3 Bitline Conditioning Bitline Conditioning! Precharge bitlines high before reads! Precharge bitlines high before reads BL bit φ bit_b BL BL bit φ bit_b BL! What if pre-charged to Vdd/? " Pros: reduces read-upset " Challenge: generate Vdd/ voltage on chip 33 34 Bitline Conditioning Sense Amplifiers! Precharge bitlines high before reads φ BL bit bit_b BL! What if pre-charged to Vdd/? " Pros: reduces read-upset " Challenge: generate Vdd/ voltage on chip! Bitlines have many cells attached " Ex: 3-kbit SRAM has 8 rows x 56 cols " 8 cells on each bitline! t pd (C/I) ΔV " Even with shared diffusion contacts, 64C of diffusion capacitance (big C) " Discharged slowly through small transistors in each memory cell (small I)! Sense amplifiers are triggered on small voltage swing V (ΔV) BL V() V PRE ΔV V() 35 Sense amp activated Word line activated t 36 6
Differential Pair Amp! Differential pair requires no clock! But always dissipates static power Clocked Sense Amp! Clocked sense amp saves power! Requires sense_clk after enough bitline swing! Isolation transistors cut off large bitline capacitance sense_b bit BL P N N P sense bit_b BL sense_clk bit bit_b isolation transistors N3 regenerative feedback sense sense_b 37 38 SRAM Read Circuit SRAM Read Circuit Differential Sense Amplifier (one per column) Differential Sense Amplifier (one per column) MP MP MA4 MA5 MA4 MA5 V NOT-C V C V NOT-C V C W BW B M Read MA φ S MA3 MA Sense Amp Gain: W BW B M Read MA φ S MA3 MA Sense Amp Gain: 39 4 SRAM Write Circuit SRAM Write Circuit WRITE CKT WRITE CKT () () () () () () () () () () W DATA WB WB OPERATION (M3 ON) W DATA WB WB OPERATION (M3 ON) 4 4 7
Column Drivers: Memory Bank Array Architecture Details 44 Column Drivers: Memory Bank Tristate Buffer! Typically used for signal traveling, e.g. bus! Ideally all devices connected to a bus should be disconnected except for active device reading or writing to bus! Use high-impedance state to simulate disconnecting Ouptut Z Z Active-high buffer 45 46 Tristate Buffer Tristate Inverters Vdd CMOS circuit 47 48 8
8x4 Memory with column decoder Read/Write Memory A (A) Column -to-4 Decoder Row Decoder 3 8x4 Memory CS -to- Decoder Column Decoder Tristate Buffer (read) D D D D3 A Rd/Wr (A) Column -to-4 Row Decoder 3 CS 8x4 Memory -to- Column Decoder D D D D3 49 5 Read/Write Memory Read/Write Memory 8x4 Memory 8x4 Memory -to-4 Row Decoder -to-4 Row Decoder A 3 A 3 Rd/Wr = Rd/Wr = (A) = Column CS -to- Column Decoder D D D D3 (A) = Column CS -to- Column Decoder D D D D3 5 5 Serial Access Memories Serial Access Memories! Serial access memories do not use an address " Shift Registers " Serial In Parallel Out (SIPO) " Parallel In Serial Out (PISO) " Queues (FIFO, LIFO) 54 9
Shift Register! Shift registers store and delay data! Simple design: cascade of registers clk Din 8 Dout Denser Shift Registers! Flip-flops aren t very area-efficient! For large shift registers, keep data in SRAM instead! Move read/write pointers to RAM rather than data " Initialize read address to first entry, write to last " Increment address on each cycle...... clk counter counter readaddr writeaddr Din dual-ported SRAM reset Dout 55 56 Serial In Parallel Out Parallel In Serial Out! -bit shift register reads in serial data! Load all N bits in parallel when shift = " After N steps, presents N-bit parallel output " Then shift one bit out per cycle clk Sin shift/load clk P P P P3 Sout P P P P3 57 58 Queues FIFO, LIFO Queues! Queues allow data to be read and written at different rates.! Read and write each use their own clock, data! Queue indicates whether it is full or empty! Build with SRAM and read/write counters (pointers)! First In First Out (FIFO) " Initialize read and write pointers to first element " Queue is EMPTY " On write, increment write pointer " If write almost catches read, Queue is FULL " On read, increment read pointer! Last In First Out (LIFO) WriteClk ReadClk " Also called a stack WriteData FULL Queue ReadData EMPTY " Use a single stack pointer for read and write 59 6
Idea Admin! Memory for compact state storage! Share circuitry across many bits! Homework 7 due tonight " Minimize area per bit # maximize density! Final Project posted after class tonight! Aggressively use: " Design and layout memory " Pass transistors, Ratioing " FOM competition for extra credit " Precharge, Amplifiers to keep area down " Handout posted before Thursday class " Due 4/4 (last day of class) " Everyone gets an extension until 5/4 " Keep in mind our final exam is on 4/3 " Leave time to study! Penn ESE 57 Spring 8 - Khanna 6 Penn ESE 57 Spring 8 - Khanna 6