EE4800 CMOS Digital IC Design & Analysis Lecture 11 SRAM Zhuo Feng 11.1
Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitryit Multiple Ports Outline Serial Access Memories 11.2
Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory Read Only Memory (RAM) (ROM) (Volatile) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM 11.3
2 n words of 2 m bits each Array Architecture If n >> m, fold by 2 k into fewer rows of more columns wordlines bitline conditioning bitlines row decod der memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m bits Good regularity easy to design Very high density if good cells are used 11.4 column circuitry it
12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 λ unit cell write bit write_b read read_b 11.5
6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline word bit bit_b 11.6
Precharge both bitlines high Then turn on wordline SRAM Read One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability word A must not flip A_b bit_b bit bit_b 1.5 N2 P1 P2 N4 1.0 word bit A N1 N3 A_b 0.5 0.0 A 0 100 200 300 400 500 600 time (ps) 11.7
word Precharge both bitlines high Then turn on wordline SRAM Read One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability N1 >> N2 N3 >> N4 A must not flip A_b bit_b bit N2 P1 P2 bit_b N4 1.5 1.0 word bit A N1 N3 A_b 0.5 A 0.0 0 100 200 300 400 500 600 time (ps) 11.8
SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter A_b word bit N2 P1 P2 bit_b N4 1.5 1.0 bit_b A A N1 N3 A_b 0.5 word 0.0 0 100 200 300 400 500 600 700 time (ps) 11.9
SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter A_b N2 >> P1 N4 >> P2 word bit N2 P1 P2 bit_b N4 1.5 1.0 bit_b A A N1 N3 A_b 0.5 word 0.0 0 100 200 300 400 500 600 700 time (ps) 11.1010
SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word med weak med A A_b strong 11.11
SRAM Column Example Bitline Conditioning φ 2 More Cells Read bit_v1f bit_b_v1f Write word_q1 bit v1f SRAM Cell bit_b v1f write_q1 data_s1 11.1212
SRAM Layout Cell size is critical: 26 x 45 λ (even smaller in industry) Tile cells sharing V DD, GND, bitline contacts GND BIT BIT_B GND VDD WORD Cell boundary 11.1313
Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS A1 A0 A1 1 1 1 8 4 word A1 A0 1/2 4 16 A0 A1 2 8 1 1 word A0 1 word0 word1 word2 word3 word0 word1 word2 word3 11.1414
Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter 11.1515
Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15 11.1616
Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing 11.1717
Bitline Conditioning Precharge bitlines high before reads φ bit bit_bb Equalize bitlines to minimize voltage difference when using sense amplifiers φ bit bit_bb 11.1818
Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline t pd (C/I) ΔV Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly l through h small transistors t (small I) Sense amplifiers are triggered on small voltage swing (reduce ΔV) 11.1919
Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 P2 N2 sense bit_bb N3 11.20
Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b 11.21
Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2k word x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers 11.22
Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A1 A2 A2 Y to sense amps and write circuits Y 11.23
Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 B0 B1 B2 B3 Y 11.24
Serial Access Memories Serial access memories do not use an address Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) 11.25
Shift Register Shift registers store and delay data Simple design: cascade of registers Watch your hold times! clk Din 8 Dout 11.26
Denser Shift Registers Flip-flops aren t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data Initialize read address to first entry, write to last Increment address on each cycle clk Din 00...00 11...11 counter co ounter readaddr dual-ported rsram writeaddr reset Dout 11.27
Tapped Delay Line A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux Ex: 0 63 stages of delay clk Din SR R32 SR R16 SR R8 SR R4 SR R2 SR R1 Dout delay5 delay4 delay3 delay2 delay1 delay0 11.28
Serial In Parallel Out 1-bit shift register reads in serial data After N steps, presents N-bit parallel output clk Sin P0 P1 P2 P3 11.29
Parallel In Serial Out Load all N bits in parallel when shift = 0 Then shift one bit out per cycle shift/load clk P0 P1 P2 P3 Sout 11.30
Queues Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) WriteClk WriteData FULL Queue ReadClk ReadData EMPTY 11.31
FIFO, LIFO Queues First In First Out (FIFO) Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer Last In First Out (LIFO) Also called a stack Use a single stack pointer for read and write 11.32