Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1
Overview: Integer Operations Internal representation unsigned integers signed integers Operations arithmetic operations bitwise operations shift operations 3 Unsigned Integers Expressed in base 2, with leading zeroes Set of values starts at zero, limited by number of bits available for storage Example: 8-bit bytes min: 00000000 0 max: 11111111 255 (2 8 1) 4 2
Assuming 16 bits: 0 0000000000000000 1 0000000000000001 2 0000000000000010 3 0000000000000011 4 0000000000000100 5 0000000000000101 6 0000000000000110 7 0000000000000111 5 Signed Integers Several different systems developed: Sign and magnitude (signed magnitude) One s complement Two s complement Half of the bit patterns are used to represent negative numbers 6 3
Two s Complement Negative representation formed by applying two s complement operation to all bits in positive representation (flip all bits, add 1) Example (assume 8 bits): +25 00011001-25 11100111 7 Two s Complement Range (assume 8 bits): max 01111111 +(2 7 1) min 10000000 -(2 7 ) One representation of zero (assume 8 bits): +0 00000000-0 00000000 8 4
Assuming 16 bits: -4 1111111111111100-3 1111111111111101-2 1111111111111110-1 1111111111111111 0 0000000000000000 +1 0000000000000001 +2 0000000000000010 +3 0000000000000011 9 Example: -21 base 10 Internal representation (8 bits): +21: 00010101 flip bits: 11101010 add 1: 1-21: 11101011 10 5
Example: -22 base 10 Internal representation (8 bits): +22: 00010110 flip bits: 11101001 add 1: 1-22: 11101010 11 Example: -0 base 10 Internal representation (8 bits): +0: 00000000 flip bits: 11111111 add 1: 1-0: 00000000 12 6
Comparison: Unsigned vs Signed unsigned twos comp 000 0 0 001 1 1 010 2 2 011 3 3 100 4-4 101 5-3 110 6-2 111 7-1 13 Summary: Signed Integers Two's complement representation used on most microprocessors In C/C++, type "int" is typically 32 bits wide ~cse420/examples/example02 14 7
Operations on Integers Arithmetic operations: addition, subtraction multiplication, division Bitwise (logical) operations: AND, OR, XOR, Shift operations: SLL, SRL, SRA, 15 Bitwise Operations Almost all processors support: AND OR XOR Some processors support additional ops: NAND, NOR ANDN, ORN, XORN 16 8
Ex: Assume 8-bit Operands 01101010 AND 01011110 01001010 01101010 OR 01011110 01111110 01101010 XOR 01011110 00110100 17 Ex: Assume 8-bit Operands A B NAND 0 0 1 0 1 1 1 0 1 1 1 0 01101010 NAND 01011110 10110101 A B NOR 0 0 1 0 1 0 1 0 0 1 1 0 01101010 NOR 01011110 10000001 18 9
Other Bitwise Operations Some processors support versions of AND, OR, XOR where the second operand is inverted: P ANDN Q = P AND ~Q P ORN Q = P OR ~Q P XORN Q = P XOR ~Q Integer circuits usually already have logic to invert the second operand (for subtraction) 19 Ex: Assume 8-bit Operands A B ANDN 0 0 0 0 1 0 1 0 1 1 1 0 01101010 ANDN 01011110 00100000 A B ORN 0 0 1 0 1 0 1 0 1 1 1 1 01101010 ORN 01011110 11101011 20 10
Bitwise Circuits Example: 8-bit AND A 7 B 7 R 7 A 6 B 6 R 6 A B 8 8 8 R A 1 B 1 R 1 A 0 B 0 R 0 21 Shift Operations Almost all processors support: SLL (shift left logical) SRL (shift right logical) SRA (shift right arithmetic) Some processors support additional ops: ROL (rotate left) ROR (rotate right) 22 11
Shift Operations Shift operations move bit patterns to the left or the right within a register. Example (assuming 8 bits): 00110011 SLL 2: 11001100 Shift count: 0 to N-1 (where N is number of bits) 23 Shift Left Logical (SLL) Move bit pattern to the left, fill with zeroes on the right. Examples (assuming 8 bits): 00110011 SLL 1: 01100110 11001010 SLL 5: 01000000 24 12
Shift Right Logical (SRL) Move bit pattern to the right, fill with zeroes on the left. Examples (assuming 8 bits): 00110011 SRL 1: 00011001 11001010 SRL 5: 00000110 25 Shift Right Arithmetic (SRA) Move bit pattern to the right, fill with copies of the sign bit on the left. Examples (assuming 8 bits): 00110011 SRA 1: 00011001 11001010 SRA 5: 11111110 SRA preserves the original sign of the value. 26 13
Shift Circuits Logarithmic shifter: for N bit register, use log 2 N levels of multiplexers Example: 8 bit register ==> 3 levels 1 st level shift 4 bits 2 nd level shift 2 bits 3 rd level shift 1 bit 27 8-bit Right Logical Shifter 28 14
Combined Shift Circuits Control signal (2 bits): No shift Shift left logical Shift right logical Shift right arithmetic 29 Rotate Operations Rotate operations move bit patterns to the left or the right within a register; bits are rotated to the other end of the register. Example (assuming 8 bits): 01110011 ROL 2: 11001101 Count: 0 to N-1 (where N is number of bits) 30 15
Rotate Left (ROL) Move bit pattern to the left; bits which move "off the end" are rotated to the right. Examples (assuming 8 bits): 10110011 ROL 1: 01100111 11001010 ROL 5: 01011001 31 Rotate Right (ROR) Move bit pattern to the right; bits which move "off the end" are rotated to the left. Examples (assuming 8 bits): 00110011 ROR 1: 10011001 11001010 ROR 5: 01010110 32 16
8-bit Right Rotator 33 8-bit Right Shifter and Rotator 34 17
Arithmetic Operations Almost all processors support: Addition Subtraction Most processors support additional ops: Multiplication Division 35 Two s Complement Addition Addition of two s complement values is the same as addition of unsigned values One approach: ripple carry addition: 00011100 carry bits 00011101 + 00010110 00110011 36 18
Full Adder Cin A B Cout S(um) 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 A B Full Adder Cout S Cin 37 Ripple-Carry Adder (4 bits) A3 B3 A2 B2 A1 B1 A0 B0 A B A B A B A B Carry Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin S S S S S3 S2 S1 S0 38 19
Example: (+5) + (+6) 00000100 (+5) 00000101 + (+6) + 00000110 ---- (+11) 00001011 39 Example: (+5) + (-6) 00000000 (+5) 00000101 + (-6) + 11111010 ---- (-1) 11111111 40 20
Example: (-5) + (-6) 11111010 (-5) 11111011 + (-6) + 11111010 ---- (-11) 11110101 41 Example: (-5) + (+6) 11111110 (-5) 11111011 + (+6) + 00000110 ---- (+1) 00000001 42 21
Summary 00000100 (+5) 00000101 (+6) + 00000110 ---- (+11) 00001011 00000000 (+5) 00000101 (-6) + 11111010 ---- (-1) 11111111 11111010 (-5) 11111011 (-6) + 11111010 ---- (-11) 11110101 11111110 (-5) 11111011 (+6) + 00000110 ---- (+1) 00000001 43 Overflow Overflow occurs when the result is too large. 01111110 01111111 + 00000010 10000001 10001110 11001111 + 10000010 01010001 Result would be OK if there were more bits available to store the sum. 44 22
Detecting Overflow Human: sign of result is different than sign of operands (overflow cannot occur if signs of operands are different) Machine: carry into most significant bit (sign bit) is different than carry out of MSB Test: C n-2 XOR C n-1 45 Examples: overflow 01111110 01111111 + 00000010 10000001 overflow 10001110 11001111 + 10000010 01010001 46 23
Examples: 00000100 (+5) 00000101 (+6) + 00000110 ---- (+11) 00001011 00000000 (+5) 00000101 (-6) + 11111010 ---- (-1) 11111111 11111010 (-5) 11111011 (-6) + 11111010 ---- (-11) 11110101 11111110 (-5) 11111011 (+6) + 00000110 ---- (+1) 00000001 47 Two s Complement Subtraction One approach: circuit to perform ripple borrow subtraction Alternative: use existing ripple carry adder A - B = A + (-B) = A + (~B + 1) Negate B by flipping all the bits, adding 1 48 24
Ex: (+5) - (+6) = (+5) + (~6+1) 1 000000011 (+5) 00000101 + (~6) + 11111001 ---- (-1) 11111111 49 Ex: (-5) - (+6) = (-5) + (~6) + 1 1 111110111 (-5) 11111011 + (~6) + 11111001 ---- (-11) 11110101 50 25
Combined Adder/Subtractor (4 bits) B3 B2 B1 B0 SUB A3 A2 A1 A0 A B A B A B A B Carry Cout FA Cin Cout FA Cin Cout FA Cin Cout FA Cin S S S S S3 S2 S1 S0 SUB control signal: 0 means Add, 1 means Subtract 51 Arithmetic Operations Assume two s complement for signed integers Addition: ripple-carry adder (or faster alternative) Subtraction: variation on addition Multiplication: sequential logic Division: sequential logic 52 26
Integer Circuits Math unit: addition and subtraction bitwise operations Shift unit: shift operations Multiply and Divide unit: multiplication and division 53 MIPS Math Unit Inputs: 32-bit operands 4-bit operation code Outputs: 32-bit result 1-bit zero flag 1-bit overflow flag 54 27