Overview of Computer Organization Chapter 1 S. Dandamudi Outline Introduction Basic Terminology and Notation Views of computer systems User s view Programmer s view Advantages of high-level languages Why program in assembly language? Architect s view Implementer s view Processor Execution cycle Pipelining RSIC and CISC Memory Basic memory operations Design issues Input/Output Interconnection: The glue Historical Perspective Technological Advances S. Dandamudi Chapter 1: Page 2 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 1
Some basic terms Introduction Computer architecture Computer organization Computer design Computer programming Various views of computer systems User s view Programmer s view Architect s view Implementer s view S. Dandamudi Chapter 1: Page 3 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Introduction (cont d) Term K (kilo) M (mega) G (giga) T (tera) P (peta) Decimal 10 3 10 6 10 9 10 12 10 15 Binary 2 10 2 20 2 30 2 40 2 50 S. Dandamudi Chapter 1: Page 4 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 2
A User s View of Computer Systems S. Dandamudi Chapter 1: Page 5 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. A Programmer s View Depends on the type and level of language used A hierarchy of languages Machine language Assembly language High-level language increasing level of abstraction Application programs Machine-independent High-level languages/application programs Machine-specific Machine and assembly languages S. Dandamudi Chapter 1: Page 6 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 3
A Programmer s View (cont d) S. Dandamudi Chapter 1: Page 7 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. A Programmer s View (cont d) Machine language Native to a processor Consists of alphabet 1s and 0s 1111 1111 0000 0110 0000 1010 0000 0000B Assembly language Slightly higher-level language Human-readable One-to-one correspondence with most machine language instructions inc count S. Dandamudi Chapter 1: Page 8 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 4
A Programmer s View (cont d) Readability of assembly language instructions is much better than the machine language instructions» Machine language instructions are a sequence of 1s and 0s Assembly Language Machine Language (in Hex) inc result FF060A00 mov class_size,45 C7060C002D00 and mask,128 80260E0080 add marks,10 83060F000A S. Dandamudi Chapter 1: Page 9 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. A Programmer s View (cont d) Assemblers translate between assembly and machine languages TASM MASM NASM Compiler translates from a high-level language to machine language Directly Indirectly via assembly language S. Dandamudi Chapter 1: Page 10 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 5
A Programmer s View (cont d) S. Dandamudi Chapter 1: Page 11 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. A Programmer s View (cont d) High-level languages versus low-level languages In C: result = count1 + count2 + count3 + count4 In Pentium assembly language: mov AX,count1 add AX,count2 add AX,count3 add AX,count4 mov result,ax S. Dandamudi Chapter 1: Page 12 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 6
A Programmer s View (cont d) Some simple high-level language instructions can be expressed by a single assembly instruction Assembly Language C inc result result++; mov size,45 size = 45; and mask1,128 mask1 &= 128; add marks,10 marks += 10; S. Dandamudi Chapter 1: Page 13 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. A Programmer s View (cont d) Most high-level language instructions need more than one assembly instruction C Assembly Language size = value; mov AX,value mov size,ax sum += x + y + z; mov AX,sum add add add mov AX,x AX,y AX,z sum,ax S. Dandamudi Chapter 1: Page 14 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 7
A Programmer s View (cont d) Instruction set architecture (ISA) An important level of abstraction Specifies how a processor functions» Defines a logical processor Various physical implementations are possible All logically look the same Different implementations may differ in» Performance»Price Two popular examples of ISA specifications SPARC and JVM S. Dandamudi Chapter 1: Page 15 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Advantages of High-Level Languages Program development is faster» High-level instructions Fewer instructions to code Program maintenance is easier» For the same reasons as above Programs are portable» Contain few machine-dependent details Can be used with little or no modifications on different types of machines» Compiler translates to the target machine language» Assembly language programs are not portable S. Dandamudi Chapter 1: Page 16 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 8
Why Program in Assembly Language? Two main reasons: Efficiency» Space-efficiency» Time-efficiency Accessibility to system hardware Space-efficiency Assembly code tends to be compact Time-efficiency Assembly language programs tend to run faster» Only a well-written assembly language program runs faster Easy to write an assembly program that runs slower than its high-level language equivalent S. Dandamudi Chapter 1: Page 17 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Architect s View Looks at the design aspect from a high level Much like a building architect Does not focus on low level details Uses higher-level building blocks» Ex: Arithmetic and logical unit (ALU) Consists of three main components Processor Memory I/O devices Glued together by an interconnect S. Dandamudi Chapter 1: Page 18 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 9
Architect s View (cont d) S. Dandamudi Chapter 1: Page 19 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Architect s View (cont d) S. Dandamudi Chapter 1: Page 20 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 10
Implementer s View Implements the designs generated by architects Uses digital logic gates and other hardware circuits Example Processor consists of» Control unit» Datapath ALU Registers Implementers are concerned with design of these components S. Dandamudi Chapter 1: Page 21 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Implementer s View (cont d) S. Dandamudi Chapter 1: Page 22 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 11
Implementer s View (cont d) S. Dandamudi Chapter 1: Page 23 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Implementer s View (cont d) S. Dandamudi Chapter 1: Page 24 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 12
Processor Execution cycle Fetch Decode Execute von Neumann architecture» Stored program model No distinction between data and instructions Instructions are executed sequentially S. Dandamudi Chapter 1: Page 25 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Pipelining Overlapped execution Increases throughput Processor (cont d) S. Dandamudi Chapter 1: Page 26 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 13
Processor (cont d) Another way of looking at pipelined execution S. Dandamudi Chapter 1: Page 27 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Processor (cont d) RISC and CISC designs Reduced Instruction Set Computer» Uses simple instructions» Operands are assumed to be in processor registers Not in memory Simplifies design Example: Fixed instruction size Complex Instruction Set Computer» Uses complex instructions» Operands can be in registers or memory Instruction size varies» Typically uses a microprogram S. Dandamudi Chapter 1: Page 28 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 14
Processor (cont d) S. Dandamudi Chapter 1: Page 29 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Processor (cont d) Variations of the ISA-level can be implemented by changing the microprogram S. Dandamudi Chapter 1: Page 30 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 15
Memory Ordered sequence of bytes The sequence number is called the memory address Byte addressable memory» Each byte has a unique address» Almost all processors support this Memory address space Determined by the address bus width Pentium has a 32-bit address bus» address space = 4GB (2 32 ) Itanium with 64-bit address bus supports» 2 64 bytes of address space S. Dandamudi Chapter 1: Page 31 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Memory (cont d) S. Dandamudi Chapter 1: Page 32 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 16
Memory (cont d) Memory unit Address Data Control signals» Read» Write S. Dandamudi Chapter 1: Page 33 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Memory (cont d) Read cycle 1. Place address on the address bus 2. Assert memory read control signal 3. Wait for the memory to retrieve the data» Introduce wait states if using a slow memory 4. Read the data from the data bus 5. Drop the memory read signal In Pentium, a simple read takes three clocks cycles» Clock 1: steps 1 and 2» Clock 2: step 3» Clock 3 : steps 4 and 5 S. Dandamudi Chapter 1: Page 34 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 17
Memory (cont d) Write cycle 1. Place address on the address bus 2. Place data on the data bus 3. Assert memory write signal 4. Wait for the memory to retrieve the data» Introduce wait states if necessary 5. Drop the memory write signal In Pentium, a simple write also takes three clocks» Clock 1: steps 1 and 3» Clock 2: step 2» Clock 3 : steps 4 and 5 S. Dandamudi Chapter 1: Page 35 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Byte Ordering S. Dandamudi Chapter 1: Page 36 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 18
Byte Ordering (cont d) Multibyte data address pointer is independent of the endianness 100 in our example Little-endian Used by Pentium Big-endian Default in MIPS and PowerPC On modern processors Configurable S. Dandamudi Chapter 1: Page 37 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Design Issues Slower memories Problem: Speed gap between processor and memory Solution: Cache memory Use small amount of fast memory Make the slow memory appear faster Works due to reference locality Size limitations Limited amount of physical memory» Overlay technique Programmer managed Virtual memory» Automates overlay management» Some additional benefits S. Dandamudi Chapter 1: Page 38 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 19
Design Issues (cont d) S. Dandamudi Chapter 1: Page 39 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Design Issues (cont d) S. Dandamudi Chapter 1: Page 40 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 20
Input/Output I/O devices are interfaced via an I/O controller Takes care of low-level operations details Several ways of mapping I/O Memory-mapped I/O» Reading and writing similar to memory read/write» Uses same memory read and write signals» Most processors use this I/O mapping Isolated I/O» Separate I/O address space» Separate I/O read and write signals are needed» Pentium supports isolated I/O Also supports memory-mapped I/O S. Dandamudi Chapter 1: Page 41 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Input/Output (cont d) S. Dandamudi Chapter 1: Page 42 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 21
Input/Output (cont d) Several ways of transferring data Programmed I/O» Program uses a busy-wait loop Anticipated transfer Direct memory access (DMA)» Special controller (DMA controller) handles data transfers» Typically used for bulk data transfer Interrupt-driven I/O» Interrupts are used to initiate and/or terminate data transfers Powerful technique Handles unanticipated transfers S. Dandamudi Chapter 1: Page 43 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Interconnection System components are interconnected by buses Bus: a bunch of parallel wires Uses several buses at various levels On-chip buses» Buses to interconnect ALU and registers A, B, and C buses in our example» Data and address buses to connect on-chip caches Internal buses» PCI, AGP, PCMCIA External buses» Serial, parallel, USB, IEEE 1394 (FireWire) S. Dandamudi Chapter 1: Page 44 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 22
Interconnection (cont d) Bus is a shared resource Bus transactions» Sequence of actions to complete a well-defined activity» Involves a master and a slave Memory read, memory write, I/O read, I/O write Bus operations» A bus transaction may perform one or more bus operations Pentium burst read Transfers four memory words Bus transaction consists of four memory read operations Bus arbitration S. Dandamudi Chapter 1: Page 45 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Historical Perspective The early generations Difference engine of Charles Babbage Vacuum tube generation Around the 1940s and 1950s Transistor generation Around the 1950s and 1960s IC generation Around the 1960s and 1970s VLSI generation Since the mid-1970s S. Dandamudi Chapter 1: Page 46 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 23
Transistor density Technological Advances Until 1990s, doubled every 18 to 24 months Since then, doubling every 2.5 years Memory density Until 1990s, quadrupled every 3 years Since then, slowed down (4X in 5 years) Disk capacities 3.5 form factor 2.5 form factor 1.8 form factor (e.g., portable USB-powered drives) S. Dandamudi Chapter 1: Page 47 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Technological Advances (cont d) S. Dandamudi Chapter 1: Page 48 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 24
Technological Advances (cont d) S. Dandamudi Chapter 1: Page 49 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. Technological Advances (cont d) Last slide S. Dandamudi Chapter 1: Page 50 To be used with S. Dandamudi, Fundamentals of Computer Organization and Design, Springer-Verlag,. 25