Choosing IP-XACT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms

Similar documents
Hardware Design and Simulation for Verification

EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools

A MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models

Abstraction Layers for Hardware Design

COdesign and power Management in PLatformbased design space EXploration. Preliminary report on run-time management

A Model-based, Single-Source approach to Design-Space Exploration and Synthesis of Mixed-Criticality Systems

Design and Verification of FPGA Applications

Modeling and SW Synthesis for

System Level Design Technologies and System Level Design Languages

Semantics-Based Integration of Embedded Systems Models

Model-Based Design for effective HW/SW Co-Design Alexander Schreiber Senior Application Engineer MathWorks, Germany

System Level Design with IBM PowerPC Models

ECE 587 Hardware/Software Co-Design Lecture 12 Verification II, System Modeling

Integrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC

The Architects View Framework: A Modeling Environment for Architectural Exploration and HW/SW Partitioning

ESE Back End 2.0. D. Gajski, S. Abdi. (with contributions from H. Cho, D. Shin, A. Gerstlauer)

Reuse MATLAB Functions and Simulink Models in UVM Environments with Automatic SystemVerilog DPI Component Generation

Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS

Hardware/Software Partitioning of Digital Systems

MARTE Based Modeling Tools Usage Scenarios in Avionics Software Development Workflows

Floating-Point to Field-Tests: A Unified Development Environment for Algorithm Research

SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS

Outline. SLD challenges Platform Based Design (PBD) Leveraging state of the art CAD Metropolis. Case study: Wireless Sensor Network

Hardware-Software Co-Design and Prototyping on SoC FPGAs Puneet Kumar Prateek Sikka Application Engineering Team

Implementing MATLAB Algorithms in FPGAs and ASICs By Alexander Schreiber Senior Application Engineer MathWorks

Ilmenau Technical University Faculty of Computer Science and Automation Department of System and Control Theory

Hardware in the Loop Functional Verification Methodology

Execution of UML models Present and Future of Research and Practice

Model driven Engineering & Model driven Architecture

Integration With the Business Modeler

The Application of SystemC to the Design and Implementation of a High Data Rate Satellite Transceiver

COdesign and power Management in PLatformbased design space EXploration. Final report on run-time management

EE382V: System-on-a-Chip (SoC) Design

Raising the Level of Development: Models, Architectures, Programs

Hardware-Software Codesign. 1. Introduction

Design Issues in Hardware/Software Co-Design

EE Embedded Systems Design

2.1 Typical IP-XACT based flow The IP-XACT standard can be applied in various parts of a typical SoC design flow as depicted in Figure 1

Philip Andrew Simpson. FPGA Design. Best Practices for Team-based Reuse. Second Edition

Workshop 1: Specification for SystemC-AADL interoperability

Modeling, Analysis and Refinement of Heterogeneous Interconnected Systems Using Virtual Platforms

Contemporary Design. Traditional Hardware Design. Traditional Hardware Design. HDL Based Hardware Design User Inputs. Requirements.

UNIFIED HARDWARE/SOFTWARE CO-VERIFICATION FRAMEWORK FOR LARGE SCALE SYSTEMS

Software Architecture

COMPLEX EMBEDDED SYSTEMS

Fast and Accurate Source-Level Simulation Considering Target-Specific Compiler Optimizations

Model-Based Design for Video/Image Processing Applications

ASIC world. Start Specification Design Verification Layout Validation Finish

CS/ECE 5780/6780: Embedded System Design

Verification of Power Management Protocols through Abstract Functional Modeling

IDesignSpec Quick Start Guide Version 3.9

RTL Coding General Concepts

Post processing techniques to accelerate assertion development Ajay Sharma

Codesign Framework. Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available in their web.

Making it Easy to Deploy the UVM by Dr. Christoph Sühnel, frobas GmbH

Applying UML Modeling and MDA to Real-Time Software Development

Hardware/Software Partitioning for SoCs. EECE Advanced Topics in VLSI Design Spring 2009 Brad Quinton

System-level co-modeling AADL and Simulink specifications using Polychrony (and Syndex)

Mixed Signal Verification Transistor to SoC

Developing AUTOSAR Compliant Embedded Software Senior Application Engineer Sang-Ho Yoon

Generation of Abstract IP/XACT Platform Descriptions from UML/MARTE for System-Level Performance Estimation

Geographical Base Registries for Flanders

Hardware-Software Codesign

ARCADIA: Model-Based Collaboration for System, Software and Hardware Engineering

CoFluent Design FPGA. SoC FPGA. Embedded. Systems. HW/SW

IRQA General Information:

Database Systems. Sven Helmer. Database Systems p. 1/567

Efficient use of Virtual Prototypes in HW/SW Development and Verification

Administrivia. ECE/CS 5780/6780: Embedded System Design. Acknowledgements. What is verification?

Reducing the cost of FPGA/ASIC Verification with MATLAB and Simulink

An introduction to CoCentric

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

Designing and Prototyping Digital Systems on SoC FPGA The MathWorks, Inc. 1

SOFTWARE DRIVES HARDWARE, LESSONS LEARNED AND FUTURE DIRECTIONS

Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms. SAMOS XIV July 14-17,

Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards

Part 2: Principles for a System-Level Design Methodology

MATLAB/Simulink 기반의프로그래머블 SoC 설계및검증

Hardware Modelling. Design Flow Overview. ECS Group, TU Wien

Model-Based Embedded System Design

VLSI Testing. Fault Simulation. Virendra Singh. Indian Institute of Science Bangalore

Component-based Engineering for Embedded Systems USA EU workshop

Comprehensive AMS Verification using Octave, Real Number Modelling and UVM

Multi-Board Systems Design

Hardware-Software Codesign. 1. Introduction

System-level simulation (HW/SW co-simulation) Outline. EE290A: Design of Embedded System ASV/LL 9/10

Boost Verification Results by Bridging the Hardware/Software Testbench Gap

Design Methodologies. Kai Huang

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience

EEL 5722C Field-Programmable Gate Array Design

Introduction to C and HDL Code Generation from MATLAB

An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench by Shaela Rahman, Baker Hughes

Early Models in Silicon with SystemC synthesis

HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips

Introduction to SystemC

Overview. Design flow. Principles of logic synthesis. Logic Synthesis with the common tools. Conclusions

On graph-based design languages for consistent multi-disciplinary models

Distributed Vision Processing in Smart Camera Networks

ECE 587 Hardware/Software Co-Design Lecture 11 Verification I

Transcription:

hoosing IP-XAT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms Emmanuel Vaumorin (Magillem Design Services)

Motivation New needs for global system integration: Less improvement of design or verification techniques More management of information and specifications exchange between teams/tools Limitations in the current usage: Expressing system specifications (architecture, timing, power, etc.) with paper or even excel sheet documents Refinement into the several subparts of hardware platform or software application decoupled from design flows omplexity of systems is growing Proposed solution entric representation of the data, using the new IEEE 1685 (IP-XAT) Backbone for federating the heterogeneous data manipulated by design or verification teams/tools Requirements traceability for critical systems In : entric description of the architecture for federating tools of the framework MDA software design tools, behavioral synthesis, optimizing cross-compilers, virtual platform generators, automatic design-space exploration tools

Motivation Improve management of a development cycle generally focused on improving every step of the process with sophisticated new technologies and using innovative languages or point tools. Nevertheless, methodology central services in areas that require complex and expensive development cycle, like So production, have identified since years that the most critical issue is mostly related to information management between the several design and verification teams involved in the global process. The raising issue with growing complexity of system is less looking for more efficiency in each design or verification process, than providing innovative solution for improving the communication links between these steps. Several teams (system architects, hardware and software designers, verification engineers, integrators, etc.) and even companies (system integrator, sub-system developers, component subcontractors) are involved in the process, all working with specific and different concepts, approach, tools, languages, etc.

Inconsistencies of specifications in process cycle All teams refer to a written specification and create from this paper documentation the appropriate representation based on their specific activity language and to create the appropriate environment for their tools set. As all those steps are performed manually: they are error prone and difficult to maintain in regards with update or modifications s focus The interpretation of these documentations is not always straight as each of the domains use specific conventions which may not be shared by the other actors A lot of possible misunderstanding, undocumented or inconsistent information and consume a lot of time and effort.

Inconsistencies of specifications in process cycle Solution = provide a centric data representation and corresponding automation mechanisms for handling and managing information through the flow because currently most of those processes implement a document-based transition of the information which leads to multiple issues: Each actor of the process has to manually translate documentation to its own specific language (UML, System, HDL, matlab ). Modifications which impact the product have to be retranslated manually into a new version of the document which needs to be propagated to upper and lower teams of the cycle. Iterations between different levels are difficult due to the fact that modifications have to be manually transmitted to the actors. The raising complexity of systems tends increase to the difficulty for the final integrators and project manager to follow changes during the project and thus to ensure a good traceability of requirements and the right implementation of the specifications.

Using a common backbone for information management s focus

Using a common backbone for information management A standard is available for answering to this issue: IP-XAT IEEE 1685 is a XML schema allowing a complete structural description of the whole HW+SW system: - functional, TLM or RTL connections - Registers and system memory map - Hierarchical dependencies - Versions and configuration management - Links with all file sets repositories ommercial solutions exist and provide a complete information backbone to cope with information exchange, synchronization and traceability. Share the same information between all the actors, use a common language to describe this information, automate the generation of multiple formats depending on the task needs, automate the update of the golden reference from multiple formats, compute impact of a modification on specifications at any level of the process, perform checks between steps. Relies on a computer readable format to exchange all those information and results in a single shared specification which will be enriched at each steps of the process. Sharing a common way to describe the exchanged information and use an automated process to extract the piece of information that is relevant for their activity and to automatically translate it into their domain languages or specific tool representations.

simulation System exploration & optimization estimation & model generation BA++ BA++ System power/performance metrics HW tasks SW tasks executable specification design space definition MDA design entry IP-XAT in the framework General Overview MARTE PIM or Matlab/ Simulink system specification in System automatically pre-optimized power controller system input stimuli HW/SW task separation & testbench generation source analysis behavioral synthesis functional, power, & timing model generation use-cases user constrained HW/SW sep. & mapping source analysis cross compilation functional, power, & timing model generation 1 virtual system generator with TLM2 interface synthesis 3 bus cycle accurate System model with self-simulating power & timing models MARTE PDM (Platform Description Model) architecture/platform description (IP-XAT) 2 4 virtual platform IP component models 6 5 design space instance parameters functional reimplementation hardware/software partitioning/separation runtime management embedded software/compiler optimizations IP platform selection & configuration memory configuration/management (static & dynamic) custom hardware synthesis constraints user visualization/ reporting tool trace analysis tool simulation trace parameters for new design space instance exploration & optimization tool 1-Import architecture specification from MARTE to IP-XAT 2-Use IP-XAT architecture description to facilitate HW/SW partitioning and application mapping 3-onsistency of architecture description is ensured along the flow 4-Generation of HW virtual platform from IP-XAT 5-Analysis or simulation reports may be linked to several configuration of architecture 6-Design Space Instance parameters may be managed in Magillem SILO linked with IP- XAT

IP-XAT in the framework General Overview IP-XAT is a XML schema for describing the HW system architecture Other schemas or UML profiles can be linked for SW architecture and application mapping Also other schemas can be created, dedicated to specific domains (verification, power, timing, PB, etc.) IP-XAT is good as centric schema as it handles the structural description of all the system, from functional level down to implementation levels, and managing the hierarchical dependencies

10 Thank you very much for your attention project partners: Project Website: http://complex.offis.de