Features High-speed access : 5/45//7 (max.) Industrial: / (max.) Commercial: 2//5/45//7 (max.) Low-power operation IDT714 Active: 7mW (typ.) Standby: 5mW (typ.) IDT714 Active: 7mW (typ.) Standby: 1mW (typ.) HIGH-SPEED 4K x 8 DUAL-PORT STATIC SRAM IDT714/ LEAD FINISH (SnPb) ARE IN EOL PROCESS - ST TIME BUY EXPIRES JUNE, 218 Fully asynchronous operation from either port Battery backup operation 2V data retention ( only) TTL-compatible; single 5V (±1%) power supply Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC product compliant to MIL-PRF-5 QML Industrial temperature range ( 4 C to + C) is available for selected speeds Green parts available, see ordering information Functional Block Diagram R/WL CEL R/WR CER OEL OER I/OL- I/O7L I/O CONTROL I/O CONTROL I/OR- I/O7R AL- A11L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER AR- A11R 272 drw 1 218 Integrated Device Technology, Inc. 1 JANUARY 218 DSC-272/17
IDT714/ Description The IDT714 is a high-speed 4K x 8 Dual-Port Static RAM designed to be used in systems where on-chip hardware port arbitration is not needed. This part lends itself to those systems which cannot tolerate wait states or are designed to be able to externally arbitrate or withstand contention when both sides simultaneously access the same Dual-Port RAM location. The IDT714 provides two independent ports with separate control, address, and I/O pi that permit independent, asynchronous access for reads or writes to any location in memory. It is the user s respoibility to eure data integrity when simultaneously accessing the same memory location from both ports. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these Dual- Ports typically operate on only 7mW of power. Low-power () versio offer battery backup data retention capability, with each port typically couming 2µW from a 2V battery. The IDT714 is packaged on either a sidebraze or plastic 48-pin DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. grade product is manufactured in compliance with MIL-PRF-5 QML, making it ideally suited to military temperature applicatio demanding the highest level of performance and reliability. Pin Configuratio (1,2,) EX AL OEL A1L A11L N/C R/WL CEL VCC CER R/WR N/C A11R A1R CEL R/WL A11L A1L OEL AL A1L A2L AL A4L A5L A6L A7L A8L A9L I/O L I/O 1L I/O 2L I/O L I/O 4L I/O 5L I/O 6L I/O 7L GND 1 48 2 4 5 6 7 8 9 1 11 12 1 14 16 17 18 19 2 21 22 2 24 IDT714P or C P48-1 (4) & C48-2 (4) 48-Pin Top View (5) 47 46 45 44 4 42 41 4 9 8 7 6 5 4 2 1 29 28 27 26 VCC CER R/WR A11R A1R OER AR A1R A2R AR A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/OR I/O2R I/O1R I/OR, 272 drw 2 A1L A2L AL A4L A5L A6L A7L A8L A9L I/OL I/O1L I/O2L I/OL EX 7 6 5 4 2 52 51 5 49 48 47 8 1 46 9 45 1 44 11 4 12 42 1 IDT714J J52-1 (4) 41 14 4 52-Pin PLCC Top View (5) 9 16 8 17 7 18 6 19 5 2 4 21 22 2 24 26 27 28 29 1 2 I/O4L AL I/O5L OEL I/O6L A1L I/O7L A11L N/C GND R/WL CEL I/OR VCC I/O1R I/O2R CER I/OR R/WR I/O4R A11R I/O5R A1R I/O6R OER OER AR A1R A2R AR A4R A5R A6R A7R A8R A9R N/C I/O7R 272 drw 1. All VCC pi must be connected to the power supply. 2. All GND pi must be connected to the ground supply.. P48-1 package body is approximately. in x 2.4 in x.18 in. C48-2 package body is approximately.62 in x 2.4 in x. in. J52-1 package body is approximately. in x. in x.17 in. L48-1 package body is approximately.57 in x.57 in x.68 in. F48-1 package body is approxiamtely. in x. in x.11 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of actual part-marking. A1L A2L AL A4L A5L A6L A7L A8L A9L I/OL I/O1L I/O2L 6 5 4 2 48 47 46 45 44 4 7 1 42 8 41 9 4 1 9 IDT714L48 or F 11 8 L48-1(4) 12 & 7 F48-1(4) 1 6 14 48-Pin LCC/Flatpack 5 Top View(5) 4 16 17 2 18 1 19 2 21 22 2 24 26 27 28 29 I/OL I/O4L I/O5L I/O6L I/O7L GND I/OR I/O1R I/O2R I/OR I/O4R I/O5R AR A1R A2R AR A4R A5R A6R A7R A8R A9R I/O7R I/O6R 272 drw 4, 2
IDT714/ Absolute Maximum Ratings (1) Symbol Rating Commercial & Industrial VTERM (2) TBIAS TSTG PT () Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation Unit -.5 to +7. -.5 to +7. V - to +1-65 to +15 o C -65 to + -65 to + o C 1.5 1.5 W Recommended Operating Temperature and Supply Voltage (1,2) Grade Ambient Temperature GND Vcc - O C to +1 O C V 5.V + 1% Commercial O C to +7 O C V 5.V + 1% Industrial -4 O C to + O C V 5.V + 1% 1. This is the parameter TA. This is the "itant on" case temperature. 272 tbl IOUT DC Output Current 5 5 272 tbl 1 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 1% for more than %of the cycle time or 1 maximum, and is limited to < 2 for the period of VTERM > Vcc +1%.. VTERM = 5.5V. Recommended DC Operating Conditio Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5. 5.5 V GND Ground V VIH Input High Voltage 2.2 6. (2) V Capacitance (1) (TA = + C, f = 1.MHz) Symbol Parameter Conditio (2) Max. Unit CIN Input Capacitance VIN = dv 11 pf VIL Input Low Voltage -.5 (1).8 V 1. VIL (min.) > -1.5V for pulse width less than 1. 2. VTERM must not exceed Vcc + 1%. 272 tbl 4 COUT Output Capacitance VOUT = dv 11 pf 272 tbl 2 1. This parameter is determined by device characterization but is not production tested. 2. dv references the interpolated capacitance when the input and output signals switch from V to V and from V to V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5V ± 1%) 714 714 Symbol Parameter Test Conditio Min. Max. Min. Max. Unit ILI Input Leakage Current (1) VCC = 5.5V, VIN = V to VCC ILO Output Leakage Current CE - VIH, VOUT = V to VCC 1 5 µa 1 5 µa VOL Output Low Voltage IOL = 6.4.4 V IOL = 8.5.5 V VOH Output High Voltage IOH = -4 2.4 2.4 V 1. At Vcc < 2.V input leakages are undefined. 272 tbl 5
IDT714/ DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (1,2) (VCC = 5.V ± 1%) 714X2 Com'l Only 714X Com'l & Ind 714X5 Com'l & Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit ICC ISB1 ISB2 ISB Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) CE = VIL Outputs Disabled f = fmax () CEL and CER = VIH f = fmax () CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fmax () Both Ports CEL and CER > VCC -.2V VIN > VCC -.2V or VIN <.2V, f = () 17 17 1..2 28 24 1 8 18 4.5 16 16 16 16 1..2 1..2 28 22 1 26 8 5 1 8 18 14 21 17 4. 1 1..2 1..2 26 21 45 17 1 2 16 4. 1 ISB4 Full Standby Current (One Port - CMOS Level Inputs) One Port CE"A" or CE"B" > VCC -.2V VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled, f = fmax () 17 1 17 12 21 16 11 19 1 272 tbl 6a 714X45 Com'l & 714X Com'l, Ind & 714X7 Com'l & Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit ICC Dynamic Operating Current (Both Ports Active) CE = VIL Outputs Disabled f = fmax () 14 14 14 14 24 2 28 24 14 14 14 14 24 2 27 22 14 14 14 14 24 2 27 22 ISB1 Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH f = fmax () 7 4 7 5 7 4 7 5 7 4 7 5 ISB2 Standby Current (One Port - TTL Level Inputs) CE"A" = VIL and CE"B" = VIH Active Port Outputs Disabled, f=fmax () 16 1 19 16 1 18 16 1 18 ISB Full Standby Current (Both Ports - CMOS Level Inputs) Both Ports CEL and CER > VCC -.2V VIN > VCC -.2V or VIN <.2V, f = () 1..2 1..2 4. 1 1..2 1..2 4. 1 1..2 1..2 4. 1 ISB4 Full Standby Current (One Port - CMOS Level Inputs) One Port CE"A" or CE"B" > VCC -.2V VIN > VCC -.2V or VIN <.2V Active Port Outputs Disabled, f = fmax () 1 18 12 1 17 12 1 17 12 1. 'X' in part number indicates power rating ( or ). 2. VCC = 5V, TA = + C for typical, and parameters are not production tested.. fmax = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = mea no address or control lines change. Applies only to inputs at CMOS level standby ISB. 272 tbl 6b 4
IDT714/ Data Retention Characteristics Over All Temperature Ranges ( Version Only) VLC =.2V, VHC = VCC -.2V Symbol Parameter Test Condition Min. Typ. (1) Max. Unit VDR VCC for Data Retention VCC = 2V 2. V ICCDR Data Retention Current CE > VHC VIN > VHC or < VLC MIL. &. 1 4 µa. 1 tcdr () Chip Dese lect to Data Retention Time tr () Operation Recovery Time trc (2) 1. VCC = 2V, TA = + C, and are not production tested. 2. trc = Read Cycle Time.. This parameter is guaranteed by device characterization, but not production tested. 272 tbl 7 Data Retention Waveform DATA RETENTION MODE VCC tcdr 4.5V VDR 2V 4.5V tr CE VIH VDR VIH 272 drw 5 AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to.v 5 1.5V 1.5V Figures 1 and 2 272 tbl 8 +5V +5V DATAOUT 1Ω DATAOUT 1Ω 7Ω pf 7Ω 5pF * 272 drw 6, 272 drw 7, Figure 1. AC Output Test Load Figure 2. Output Test Load (for tlz, thz, twz, tow) *Including scope and jig 5
IDT714/ AC Electrical Characteristics Over the Operating Temperature and Supply Voltage () 714X2 Com'l Only 714X Com'l & Ind 714X5 Com'l & Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 2 5 taa Address Access Time 2 5 tace Chip Enable Access Time 2 5 taoe Output Enable Access Time 2 toh Output Hold from Address Change tlz Output Low-Z Time (1,2) thz Output High-Z Time (1,2) 2 tpu Chip Enable to Power Up Time (2) tpd Chip Disable to Power Down Time (2) 2 5 272 tbl 9a 714X45 Com'l & 714X Com'l, Ind & 714X7 Com'l & Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 45 7 taa Address Access Time 45 7 tace Chip Enable Access Time 45 7 taoe Output Enable Access Time 4 toh Output Hold from Address Change tlz Output Low-Z Time (1,2) 5 5 5 thz Output High-Z Time (1,2) 2 tpu Chip Enable to Power Up Time (2) tpd Chip Disable to Power Down Time (2) 45 5 5 1. Traition is measured mv from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested.. 'X' in part number indicates power rating ( or ). 272 tbl 9b 6
IDT714/ Timing Waveform of Read Cycle No. 1, Either Side (1,2,4) ADDRESS trc toh taa (5) toh DATAOUT PREVIOUS DATA VALID DATA VALID 272 drw 8 Timing Waveform of Read Cycle No. 2, Either Side (1,) tace CE taoe (4) thz (2) OE tlz (1) thz (2) DATAOUT VALID DATA (4) ICC CURRENT ISB tpu 5% tlz (1) tpd 5% 272 drw 9 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first, OE or CE.. R/W = VIH. 4. Start of valid data depends on which timing becomes effective, taoe, tace or taa 5. taa for RAM Address Access and ta for Semaphore Address Access. 7
IDT714/ AC Electrical Characteristics Over the Operating Temperature and Supply Voltage (5) 714X2 Com'l Only 714X Com'l & Ind 714X5 Com'l & Symbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE twc Write Cycle Time 2 5 tew Chip Enable to End-of-Write 2 taw Address Valid to End-of-Write 2 tas Address Set-up Time twp Write Pulse Width 2 twr Write Recovery Time tdw Data Valid to End-of-Write 2 thz Output High-Z Time (1,2) 2 tdh Data Hold Time () twz Write Enable to Output in High-Z (1,2) 2 tow Output Active from End-of-Write (1,2,) twdd Write Pulse to Data Delay (4) 4 5 6 tddd Write Data Valid to Read Data Delay (4) 5 272 tbl 1a 714X45 Com'l & 714X Com'l, Ind & 714X7 Com'l & Symbol Parameter Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE twc Write Cycle Time 45 7 tew Chip Enable to End-of-Write 4 5 6 taw Address Valid to End-of-Write 4 5 6 tas Address Set-up Time twp Write Pulse Width 4 5 6 twr Write Recovery Time tdw Data Valid to End-of-Write 2 thz Output High-Z Time (1,2) 2 tdh Data Hold Time () twz Write Enable to Output in High-Z (1,2) 2 tow Output Active from End-of-Write (1,2,) twdd Write Pulse to Data Delay (4) 7 8 9 tddd Write Data Valid to Read Data Delay (4) 45 7 272 tbl 1b 1. Traition is measured mv from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested.. The specification for tdh must be met by the device supplying write data to the RAM under all operating conditio. Although tdh and tow values will vary over voltage and temperature, the actual tdh will always be smaller than the actual tow. 4. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read. 5. 'X' in part number indicates power rating ( or ). 8
IDT714/ Timing Waveform of Write with Port-to-Port Read (1,2,) twc ADDR "A" MATCH R/W "A" (1) twp taw tdw DATAIN "A" VALID ADDR "B" MATCH twdd DATAOUT "B" 1. Write cycle parameters should be adhered to, in order to eure proper writing. 2. CEL = CER = VIL. OE"B" = VIL.. Port "A" may be either left or right port. Port "B" is the opposite from port "A". tddd VALID 272 drw 1 Timing Waveform of Write Cycle No. 1, R/W Controlled Timing (1,5,8) ADDRESS twc OE tas (6) taw twr () CE (2) twp (7) thz R/W (7) tlz twz (7) tow thz (7) DATAOUT (4) (4) tdw tdh DATAIN 272 drw 11 1. R/W or CE must be HIGH during all address traitio. 2. A write occurs during the overlap (tew or twp) of a CE =VIL and R/W = VIL.. twr is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle. 4. During this period, the I/O pi are in the output state, and input signals must not be applied. 5. If the CE = VIL traition occurs simultaneously with or after the R/W = VIL traition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal (CE or R/W) is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Traition is measured mv from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of twp or (twz + tdw) to allow the I/O drivers to turn off data to be placed on the bus for the required tdw. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified twp. 9
IDT714/ Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,4) ADDRESS CE taw twc tas (5) tew (2) twr () R/W tdw tdh DATAIN 272 drw 12 1. R/W or CE must be HIGH during all address traitio. 2. A write occurs during the overlap (tew or twp) of a CE =VIL and R/W = VIL.. twr is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle. 4. If the CE LOW traition occurs simultaneously with or after the R/W LOW traition, the outputs remain in the High-impedance state. 5. Timing depends on which enable signal (CE or R/W) is asserted last. Functional Description The IDT714 provides two ports with separate control, address, and I/O pi that permit independent access for reads or writes to any location in memory. These devices have an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Each port has its own Output Enable control (OE). In the read mode, the port s OE tur on the output drivers when set LOW. Non-contention READ/WRITE conditio are illustrated intruth Table I. Truth Table I Read/Write Control Left or Right Port (1) R/W CE OE D-7 Function X H X Z Port Deselected and in Power-Down Mode, ISB2 or ISB4 X H X Z CER = CEL = H, Power Down Mode ISB1 or ISB L L X DATAIN Data on port written into memory H L L DATAOUT Data in memory output on port X X H Z High impedance outputs NOTE: 1. AL - A11L AR - A11R "H" = VIH, "L" = VIL, "X" = Don t Care, and "Z" = High Impedance 272 tbl 11 1
IDT714/ Ordering Information XXXX A 999 A A A Device Type Power Speed Package Process/ Temperature Range A Blank 8 Blank I (1) B G (2) P C J L F () 2 5 45 7 Tube or Tray Tape and Reel Commercial ( C to +7 C) Industrial (-4 C to + C) (- C to +1 C) Compliant to MIL-PRF-5 QML Green 48-pin Plastic DIP (P48-1) 48-pin Ceramic DIP (C48-2) 52-pin PLCC (J52-1) 48-pin LCC (L48-1) 48-pin Ceramic Flatpack (F48-1) Commercial Only Commercial & Industrial Commercial & Commercial & Commercial, Industrial & Commercial & Low Power Standard Power Speed in nanoseconds 714 1. Contact your local sales office for industrial temp. range for other speeds, packages and powers. 2. Green parts available. For specific speeds, packages and powers contact your local sales office. LEAD FINISH (SnPb) parts are in EOL process. Product Discontinuation Notice - PDN# SP-17-2. For "P", plastic DIP, when ordering green package the suffix is "PDG". 2K (4K x 8-Bit) Dual-Port RAM 272 drw 1 Datasheet Document History //99: Initiated datasheet document history Converted to new format Cosmetic and typographical correctio Pages 2 Added additional notes to pin configuratio 6/9/99: Changed drawing format 1/1/99: Added Industrial Temperature Ranges and removed corresponding notes 11/1/99: Replaced IDT logo 12/22/99: Page 1 Made correctio to drawing //: Corrected block diagram and pin configuratio Changed ±5mV to mv 1/12/: Pages 1 2 Moved "Description to page 2 and adjusted page layout Page 1 Added " only)" to paragraph Page 2 Fixed P48-1 package description Page Increased storage temperature parameters Clarified TA parameter Page 4 DC Electrical parameters changed wording from "open" to "disabled" Page 1 Fixed Truth Table specification in "Functional Description" paragraph 1/17/6: Page 1 Added green availability to features Page 11 Added green indicator to ordering information Page 1 & 11 Replaced old IDTTM with new IDTTM logo 8/12/8: Page 11 Corrected typo in the ordering information 11
IDT714/ Datasheet Document History (con't.) 1/21/8: Page 11 Removed "IDT" from orderable part number 2/4/1: Page 1, 4, 6 & 8 Removed & Industrial 5 speed grades from Features and corrected the headers of the DC Chars and AC Chars tables to indicate this change Page 11 Added T& R indicator to and removed & Industrial 5 speed grades from the ordering information 1/11/18: Page 2 Typo/correction Product Discontinuation Notice - PDN# SP-17-2 Last time buy expires June, 218 CORPORATE HEADQUARTERS for LES: for Tech Support: 624 Silver Creek Valley Road 8-45-7 or 48-284-82 48-284-2794 San Jose, CA 18 fax: 48-284-27 DualPortHelp@idt.com www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 12