Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals Final Exam Solution Sunday, December 15, 10:05-12:05 PM Fall 2002 Instructions: 1. Closed book examination. 2. No calculator, hand-held computer or portable computer allowed. 3. Five points penalty if you fail to enter name, ID#, or instructor selection. 4. Answer must be entered into specified boxes if provided. 5. You must show your work to receive full or partial credit for your answers. 6. No one shall leave room during last 5 minutes of the examination. 7. Upon announcement of the end of the exam, stop writing on the exam paper immediately. Pass the exam to isles to be picked up by a TA. The instructor will announce when to leave the room. 8. Failure to follow instructions may result in forfeiture of your exam and will be handled according to UWS 14 Academic misconduct procedures. Flip-Flop Excitation Tables JK Flip-Flop SR Flip-Flop Q(t) Q(t+1) J K Q(t) Q(t+1) S R 0 0 0 X 0 0 0 X 0 1 1 X 0 1 1 0 1 0 X 1 1 0 0 1 1 1 X 0 1 1 X 0 D Flip-Flop T Flip-Flop Q(t) Q(t+1) D Q(t) Q(t+1) T 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 F02, ECE/CS 352 Quiz #3 1
1. (10 points) 2-level implementation and logic minimization (a) (5 points) Implement the following Boolean functions in 2-level NOR-NOR logic. F(a, b, c, d) = m(1, 3, 5, 7, 9, 12, 15). Minimize your logic and draw the logic schematic. Assume complements of the input Boolean variables are available. Answer: To find NOR-NOR implementation, we need to find F ( a, b, c, d) in SOP format, which is F ( a, b, c, d) = a d + b d + c d + a b c + a b c d. Then we find F(a, b, c, d) by finding a dual of F ( a, b, c, d), the complementing each literals. F ( a, b, c, d) = ( a + d) ( b + d) ( c + d) ( a + b + c) ( a + b + c + d) a d b d c d a b a c b c d (b) (5 points) Consider the Boolean function below: F(a, b, c, d) = M (1, 4, 5, 6, 9, 10). Find ALL the prime implicants of function f(a, b, c, d) using the tabular method. Answers without work will not receive any credit! Answer: 0000 G0 0000 G0-G1 00-0 0010 G1 0010-000 0011 1000 G1-G2 001-0111 G2 0011 1-00 1000 1100 G2-G3 0-11 G2-G3-G4 --11 1011 G3 0111-011 11-- 1100 1011 110-1101 1101 11-0 1110 1110 G3-G4-111 1111 G4 1111 1-11 11-1 111- F(a, b, c, d) PIs are all the cubes without check marks next to them; they are 00-0, -000, 001-, 1-00, --11 and 11-- (in cube notation), or a b d, b c d, a b c, a c d, c d, and a b. ECE/CS 352 Final Fall 2002 2
2. (10 points) Radix and Diminished-Radix arithmetic Compute the following using specified method (number of bits n = 6). If an overflow occurs, indicate how you have determined the overflow condition. You must show your work to receive full credit (show carries or borrows on top of minuends whenever possible). (a) (4 points) Compute the following using a signed 1 s complement arithmetic (number of bits n = 6). Since we get an end around carry, we need to add 1 to complete the subtraction (-18 10-9 10 =-27 10 ) 1111000 101101 + 110110 1100011 +1 100100 (b) (4 points) Compute the following using an unsigned 2 s complement arithmetic (number of bits n = 6). 0011110 001101 + 100111 0110100 Take 2 s complement, and put a minus sign (001100) (c) (2 points) Compute the following using 9 s complement arithmetic. Two numbers given below are decimal numbers. 273 10 + 231 10 0504 Take 9 s complement, and put a minus sign (495) ECE/CS 352 Final Fall 2002 3
3. (10 points) ALU A 4-bit multi-function register operates according to a function table where S 1, S 0 are two mode selection inputs. Full Adder S1 A i X Y Sum Cout F i C i+1 B i S0 Ci Cin The schematic above is an ALU bit slice which can perform both arithmetic and logic operations by choosing appropriate control signals C 0, S 0 and S 1 where C 0 is a C i for the least significant bit.. Let F = F n 1 F 1 F 0 to be the output, A = A n 1 A 1 A 0 and B = B n 1 B 1 B 0. Complete the function table below for output F. For each function, clearly indicate whether the function is an arithmetic operation (A) or a logical operation (L). Answer: S0 determines logical (S0=0) or arithmetic (S0=1) operation. The combinational circuit feeding Y is a 2-to-1 multiplexer and S1 is a select signal; S1 simply selects B (when S1=0) or B (when S1=1). Now, it just a matter of figuring out what inputs are placed on Cin and Y to determine the function of the ALU. S 1 S 0 C 0 = 0 C 0 = 1 0 0 A B, (L) A B, (L) 0 1 A + B, (A) A+ B+1, (A) 1 0 A B, (L) A B, (L) 1 1 A B (in 1 s complement =A+ B ) (A) A B (in 2 s complement =A+ B +1) (A) ECE/CS 352 Final Fall 2002 4
4. (10 points) Sequential circuits and timing analysis The clock (CLK) signal is connected to following two sequential circuits with output Y. D-Latch A B Y CLK SR-Latch SR-Latch The clock (CLK) signal is connected to a sequential circuit with output Y. Complete the timing diagram given below. Assume that the gate delays are negligible. Answer: The circuit shown above is simply a negative edge triggered JK flip-flop. Notice that it is consists of one SR-latch (a 4-NAND gate network), one D-latch (SR-latch with an input feeding S and inverted input feeding R), and simple three gate network to implement, hold, reset, set and toggle. The timing diagram of a negative edge triggered JK flip-flop should be as follows. CL K A B Y 5. (15 points) State diagram, state table and synchronous circuit design The state diagram shown below is for a synchronous sequential circuit with unknown function. This sequential circuit has two state variables S1(t) and S0(t), and an input C. State variables S1(t) and S0(t) are to be implemented with SR flip-flops. C=0/Z=0 C=0/Z=0 C=1/Z=1 11 00 C=1/Z=0 C=1/Z=0 10 01 C=1/Z=0 C=0/Z=0 C=0/Z=0 ECE/CS 352 Final Fall 2002 5
(a) (5 points) Complete the state table below. Answer: This is a simple 2-bit counter with enable input, C (C=0: hold, C=1: count) and one output Z to signal 11 to 00 transition. C S1(t) S0(t) S1(t+1) S0(t+1) Z S1 S S1 R S0 s S0 R 0 0 0 0 0 0 0 X 0 X 0 0 1 0 1 0 0 X X 0 0 1 0 1 0 0 X 0 0 X 0 1 1 1 1 0 X 0 X 0 1 0 0 0 1 0 0 X 1 0 1 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 X 0 1 0 1 1 1 0 0 1 0 1 0 1 (b) (4 points) Express the result in a minimized SOP standard format. S1 S = C S 1 S0 S1 R = C S 1 S0 S0 S = C S0 S0 R = C S0 (c) (3 points) A set-dominant SR flip-flop is a special type of SR flip-flop such that when both inputs S and R are set to logic 1, the output of the FF becomes logic 1 in the next clock cycle. Suppose you are to use a pair of set-dominant SR flip-flops to implement the circuit. Would this change your implementation/design? Answer: (circle only one) Yes or No If Yes, list all implementation/design changes. If No, show why it would not change your implementation. You must show your work to get credit. If set-dominant SR flip-flops are used, then to change present state from Q(t)=0 to Q(t+1)=1, we should set S=1, R=X (different from normal SR flip-flop s, S=1, R=0). This changes our design/implementation since few state table entries for R inputs include additional don t cares (X s). Thus S1 R and S0 R change as shown below. ECE/CS 352 Final Fall 2002 6
S1 S = C S 1 S0 S1 R = C S0 S0 S = C S0 S0 R = C (d) (3 points) A reset-dominant SR flip-flop is a special type of SR flip-flop such that when both inputs S and R are set to logic 1, the output of the FF becomes logic 0 in the next clock cycle. Suppose you are to use a pair of reset-dominant SR flip-flops to implement the circuit. Would this change your implementation/design? Answer: (circle only one) Yes or No If Yes, list all implementation/design changes. If No, show why it would not change your implementation. You must show your work to get credit. If reset-dominant SR flip-flops are used, then to change present state from Q(t)=0 to Q(t+1)=1, we should set S=X, R=1 (different from normal SR flip-flop s, S=0, R=1). This changes our design/implementation since few state table entries for S inputs are to include additional don t cares (X s). Thus S1 S and S0 S change as shown below. S1 S = C S0 S1 R = C S 1 S0 S0 S = C S0 R = C S0 6. (5 points) Memory organization (a) (3 points) How many address lines and how many data lines a 128K 8 SRAM chip has? Answer: 128K= 128*1024 = 2 7 *2 10 = 2 7+10 = 2 17 Number of address lines = 17 ECE/CS 352 Final Fall 2002 7
Number of data lines = 8 (b) (2 points) How many 64K 8 SRAM chips are required to build a 128K 32 SRAM subsystem? 128K/64K * 32/8 = 2 * 4 =8 8 chips 7. (20 points) Programmable Devices and Hazard. Following is a programmed Programmable Logic Array implementing three functions F(A, B, C), G(A, B, C) and H(A, B, C). For the remaining of this problem, we will focus only on F(A, B, C). Warning: There will be NO partial credit given for this problem. A B C F G H (a) (4 points) Draw a Karnaugh map corresponding to the function F(A, B, C) and show all product terms used for implementing function F(A, B, C). A\BC 00 01 11 10 0 1 1 1 1 1 0 1 1 0 ECE/CS 352 Final Fall 2002 8
(b) (4 points) Redraw a Karnaugh map corresponding the function F(A, B, C) and indicate all single input change static-1 hazard. There are four pairs of single input change static-1 hazard, total 8 possible single input changes. Answer: A\BC 00 01 11 10 0 1 1 1 1 1 0 1 1 0 (c) (4 points) A multiple input change logic hazard may occur. Identify all of them by filling the blanks of the table below. Answer: A multiple input change logic hazard indicate the hazard that can be fixed by adding logic(s). There are two pairs of two-input change logic 1 hazard as shown below. Thus we have followings: A\BC 00 01 11 10 0 1 1 1 1 1 0 1 1 0 Input before a multiple input change Input after a multiple input change A B C A B C 0 0 1 1 1 1 1 1 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 (d) (3 points) Suppose you are to use the fewest number of additional product terms (AND gates) to be ORed to the function F to eliminate all logical hazards. List the function F below using a SOP standard notation. Hint: List the original product terms used first, then list the additional product terms required to eliminate the static-1 logic hazard. Answer: F(A, B, C) = A B + A B + A C + A + C (e) (5 points) Implement the function Z ( a, b, c) = a b c + a b c + a b c + a b c using Programmable Array Logic below. Be sure to label all inputs and clearly indicate the output Z. Answers: Since you are not asked to minimize the logic, you can either use given expression directly or minimize Z to use only one output. Below, we perform a direct implementation of the given function and unused cells are programmed to be 0 (shown in red X). Notice that ECE/CS 352 Final Fall 2002 9
X s in the AND gates indicate that all of their inputs are fused so that they output a logic 0 all the time. a Z b c 8. (15 points) Below is an ASM chart of certain controller. Assume R0 and R1 are 8-bit registers. R0 R0+1 IDLE 1 0 S R1 0 WORK R0 0 R1 R1+1 0 C 1 ECE/CS 352 Final Fall 2002 10
(a) (5 points) Find the response for the ASM chart above to the following sequence of inputs (assume that the initial state is ST0). Answer: S: 1 1 1 0 0 0 0 0 1 C: 0 0 0 1 1 1 1 1 0 State: ST0 ST0 ST0 ST0 ST1 ST1 ST1 ST1 ST1 ST0 R0 0 01 h 02 h 03 h 03 h 03 h 03 h 03 h 03 h 00 h R1 0 00 h 00 h 00 h 00 h 01 h 02 h 03 h 04 h 04 h (b) (10 points) Implement this ASM chart using one-state-per-state method. Using positive edge triggered flip-flops, AND, OR, NOT gates. Simplify the design to use as few logic gates as possible. S Condition: R0 R0+1 D ST0 Condition: R1 0 C Condition: R1 R1+1 D ST1 Condition: R0 0 ECE/CS 352 Final Fall 2002 11