DDR & DDR2 SDRAM Controller Compiler

DDR & DDR2 SDRAM Controller Compiler November 2005, Compiler Version 3.2.0 Errata Sheet Introduction This document addresses known errata and documentation changes for version 3.2.0 of the DDR & DDR2 SDRAM Errata are design functional defects or errors. Errata may cause the DDR & DDR2 SDRAM Controller Compiler to deviate from published specifications. Documentation changes include typos, errors, unclear descriptions or omissions from current published specifications or product documents. These documentation changes or clarifications will be incorporated into an upcoming release of the DDR & DDR2 SDRAM DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues Altera has identified the following issues that affect the DDR & DDR2 SDRAM Controller Compiler v3.2.0: 1. DDR SDRAM Controller Write Data Slip Errors on page 2 2. Clock Pin Names Must End In [0] on page 3 3. Creating Custom Variations In Directories Other Than The Quartus II Project Directory on page 3 4. DDR or DDR2 SDRAM Controller Version 3.2.0 Cyclone II Devices in a Quartus II v5.1 Project on page 4 5. SOPC Builder System Generation Fails on page 14 6. Post-Compilation Timing Analysis Is Not Supported on Stratix II Advanced Devices on page 5. 7. Incorrect Postamble Register Placements (Cyclone II Devices Only) on page 6. 8. Non-DQS, Non-Migratable Floorplans Contain Only Sidebank Pins on page 7. 9. Error Message When Recompiling a Project on page 8. 10. Remove Redundant Logic Cells Option (Stratix Devices Only) on page 8. Altera Corporation 1 ES-042705-1.1

DDR & DDR2 SDRAM Controller Compiler 11. SOPC Builder Supported Memory Data Bus Widths on page 9. 12. Errors After Creating Multiple Controllers in the Same Directory on page 10. 13. Precompile Timing Estimates With Four or More DQS Delay Matching Buffers (Stratix Devices Only) on page 11. 14. Illegal Byte Group Placements (Stratix & Stratix GX devices only) on page 11. 15. DQS I/O Pin Error (Cyclone Devices Only) on page 12. 16. Design Assistant Warning Messages on page 13. DDR SDRAM Controller Write Data Slip Errors Under some circumstances, the DDR SDRAM Controller may issue a write command to the memory before the write data is available to be written. This issue causes a write data slip the same data is written to two consequetive locations and all subsequent writes receive the data intended for the previous location. This issue affects only DDR SDRAM Controllers configured to use the native interface and a memory burst length of 4 or 8. DDR2 SDRAM designs and designs that use the Avalon interface or a memory burst length of 2 are unaffected. This issue leads to the controller writing incorrect data to the memory. To prevent this error from occuring, turn on Insert extra pipeline registers on address and command outputs on the IP Toolbench Controller Settings tab. This issue will be fixed in a future release of the DDR and DDR2 SDRAM controller. 2 Altera Corporation

DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues Clock Pin Names Must End In [0] In IP Toolbench, if you edit the pin names of the clocks driving the memory and remove the [0] from the end of the clock name, the postcompile timing verification script fails with the following error message: Error: Timing node '<clock pin name>_out' (pin name = '<clock pin name>') cannot be found The clock pin names must have a [0] on the end of their names, even if you select to have more than one clock pair from the FPGA to the memory. However, the fed-back clock name does not require a [0] on the end of the name. This issue affects any variation where you have edited the pin names of the clocks and not added a [0] to the end of the names. The post-compile timing verification script cannot analyze your design. Replace the [0] on the clock pin names. This issue will be fixed in a future release of the DDR and DDR2 SDRAM controller. Creating Custom Variations In Directories Other Than The Quartus II Project Directory If you create your controller variation in a directory other than the Quartus II project directory, the automatic add constraints and verify timing scripts do not run properly. You receive the following error message when trying to compile the project: Error: Tcl Script File auto_add_ddr_constraints.tcl not found If you move the project after you have successfully compiled it, you will receive the following error message: Error: Tcl Script File auto_verify_ddr_timing.tcl not found Altera Corporation 3

DDR & DDR2 SDRAM Controller Compiler This issue affects all designs where the variation is not created in the Quartus II project directory. You cannot successfully add constraints to or verify the timing of your design. Copy the automatic add constraints (auto_add_ddr_constraints.tcl) and automatic verify timing script (auto_verify_ddr_timing.tcl) into the Quartus II project directory. Edit the scripts and add the correct path to the location of the constraints and timing scripts for each variation listed. This issue will be fixed in a future release. DDR or DDR2 SDRAM Controller Version 3.2.0 Cyclone II Devices in a Quartus II v5.1 Project If you attempt to use the verify timing script of a DDR or DDR2 SDRAM Controller v3.2.0 with a Cyclone II device in a Quartus II v5.1 project, you will encounter the following error. ASSERTION FAILED( [get_timing_node_info -info type $dqsnode] == "clk" ) Tracking back from dq pin to dqs pin didn't get to a node of type clk. This issue affects all Cyclone II designs created with the DDR or DDR2 SDRAM controller v3.2.0, which are compiled in the Quartus II software v5.1. The verify timing script fails to report any timing margins. You should upgrade to DDR & DDR2 SDRAM Controller v3.3.0, if you are using the Quartus II software v5.1. 4 Altera Corporation

DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues This issue will never be fixed. SOPC Builder System Generation Fails In the SOPC Builder flow, if you use a dedicated resynchronization clock for the DDR2 SDRAM controller, the SOPC Builder generation fails with the following error message: Error: Test Generator Program for module 'ddr_sdram' did NOT run successfully. This issue affects the DDR2 SDRAM controller when you use the SOPC builder flow and use a dedicated resynchronization clock. SOPC Builder generation fails. There are two workarounds. You can run the system in a single clock domain. Or locate and change the following line in the generate_ddr_sim_model.pl file in the \lib\sopc_builder\ddr2_sdram_component\ directory: my $number_of_lump_delays = ($rtl_sim_delay / ($clockperiod / 4) + 1); Change it to the following code: my $number_of_lump_delays = floor($rtl_sim_delay / ($clockperiod / 4) + 1); This issue will be fixed in the next version of the DDR and DDR2 SDRAM Post-Compilation Timing Analysis Is Not Supported on Stratix II Advanced Devices If you turn on Show Advanced Devices in the Quartus II New Project Wizard for Stratix II devices, it lists the following advanced devices: Altera Corporation 5

DDR & DDR2 SDRAM Controller Compiler EP2S90H484 EP2S90F780 EP2S130F780 The device package information for the Stratix II advanced devices is not available in the Quartus II software version 5.0. You can still create either a DDR or DDR2 SDRAM MegaCore function variation that is targeted at Stratix II advanced devices. However, when you compile your design, the verify timing script fails with the following error message: Error: Cannot find source node 'ddr_dqs[0]_in' Error: Extractions stopped due to error This issue affects all DDR and DDR2 SDRAM Controller MegaCore functions generated for Stratix II advanced devices. You cannot run post-compilation timing analysis for designs on Stratix II advanced devices in the Quartus II software version 5.0. Also you cannot set constraints for EP2S90H484 devices. Target your design to a device that is not on the Advanced Devices list. This issue will be fixed in a future release of the DDR and DDR2 SDRAM Controller Compiler, once the package information is available in a future version of the Quartus II software. Incorrect Postamble Register Placements (Cyclone II Devices Only) The automatic constraints on the postamble registers place them close to the DQS pins. On Cyclone II devices, they should be close to the clock control blocks. This issue produces negative setup slack on the read postamble enable path, which is reported by the verify timing script when you compile the design. This issue affects all configurations targeted at Cyclone II devices. 6 Altera Corporation

DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues This issue may lead to functional errors when operating. Manually re-assign the critical registers (dq_enable[0] and dq_enable_reset[0]) for each byte group to be close to the clock control block that they feed. f For assistance with this change, contact Altera. Altera provides a script to automatically correct the constraints for the following three Altera Cyclone II development boards: Cyclone II EP2C35 DSP Development Board Cyclone II EP2C35 PCI Development Board Nios Development Board, Cyclone II Edition In the Quartus II software, choose Tcl Scripts (Tools menu) and run the Tcl script, fix_ep2c35f672_postamble_constraints.tcl, which is in the ddr_ddr2_sdram-v3.2.0\lib directory. This issue will be fixed in the next version of the DDR and DDR2 SDRAM Non-DQS, Non-Migratable Floorplans Contain Only Sidebank Pins If you choose not to use DQS to capture your read data and to use non-migratable DQ, DQS, and DM pins on Stratix II devices, the constraints plug-in does not display any available byte groups on the top and bottom edges of the device. This issue affects all designs targeted at Stratix II devices when you turn off Use DQS for read capture and turn on Use non-migratable DQ, DQS, and DM pins in IP Toolbench. You cannot target the top or bottom pins on the device. Altera Corporation 7

DDR & DDR2 SDRAM Controller Compiler Use DQS for read capture or use migratable pins. For more information on the recommended pins to use in this mode on these edges, contact Altera. Error Message When Recompiling a Project If you move the directory containing your Quartus II project, or rename your Quartus II project and recompile it without regenerating the DDR or DDR2 SDRAM Controller, you may receive the following error: Error: DDR timing cannot be verified until project has been successfully compiled. This error indicates that some of the settings files contain references to the previous location or project name and the verify timing script is unable to find the current project. This issue affects all configurations. The timing script does not verify your design. Regenerate your controller in IP Toolbench and recompile the project. The timing analysis script now completes correctly. This issue will be fixed in a future version of the DDR and DDR2 SDRAM Remove Redundant Logic Cells Option (Stratix Devices Only) Do not turn on Remove Redundant Logic Cells in the Quartus II software if you are targeting Stratix devices. 8 Altera Corporation

DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues This issue affect all designs targeted at Stratix devices, if you turn on Remove Redundant Logic Cells in the Quartus II software. For Stratix devices, removing redundant logic cells makes the Quartus II software optimize away the important DQS delay matching buffers that the postamble circuitry uses. Ensure you turn off Remove Redundant Logic Cells in the Quartus II software if you are targeting Stratix devices. There are no plans to fix this issue. SOPC Builder Supported Memory Data Bus Widths SOPC Builder currently only supports data bus widths that are a power of 2. IP Toolbench does not impose these limitations in the SOPC Builder flow, and can therefore generate bus widths incompatible with SOPC builder, which results in the following error message during SOPC Builder system generation. ERROR: slave data width (48) for slave ddr_sdram/s1 unexpected This issue affects all configurations that specify data bus widths that are not a power of 2 when you use the SOPC Builder flow. You cannot generate the design in SOPC Builder. Ensure you restrict the data bus width parameter in the DDR SDRAM Controller IP Toolbench to a power of 2, for example, 8, 16, 32 or 64. Altera Corporation 9

DDR & DDR2 SDRAM Controller Compiler This issue will be fixed in the next version of the DDR and DDR2 SDRAM Errors After Creating Multiple Controllers in the Same Directory If you generate multiple controller variations in the same Quartus II project directory and your top-level design file does not instantiate all of them, the Quartus II precompilation processing step issues the following error: Error: Either Analysis & Elaboration failed or the script could not find your variation. You also see the following related error during the post compilation processing step: Error: Post compile timing analysis failed (retcode=1) These errors are caused by extra entries in the auto_add_ddr_constraints.tcl and auto_verify_ddr_timing.tcl script files. IP Toolbench adds an entry to these files each time it generates a variation, if you turn on Automatically run add constraints script or Automatically run verify timing script. However, it does not correctly remove the entry for the variation, if it is no longer instantiated in your top-level design file. 1 These errors also occur if you rename and regenerate a DDR or DDR2 SDRAM Controller component in SOPC Builder after you have generated the system at least once. This issue affects all configurations. There is no design impact. You must always edit the auto_add_ddr_constraints.tcl and auto_verify_ddr_timing.tcl script files to remove any of the following lines for variations that are no longer instantiated in your design: source add_constraints_for_<variation name>.tcl source verify_timing_for_<variation name>.tcl 10 Altera Corporation

DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues Alternatively, turn off Automatically run verify timing script and Automatically run add constraints script and run the scripts manually. There are no plans to fix this issue. Precompile Timing Estimates With Four or More DQS Delay Matching Buffers (Stratix Devices Only) For Stratix devices, if you turn on Manual postamble control and choose 4 or more for the Number of DQS delay matching buffers, the precompile timing estimates in the system timing report for the read postamble enable property are incorrect. The correct timing analysis result is shown in the post-compile timing analysis report after compiling the design in the Quartus II software. This issue affects designs on Stratix devices that require four or more DQS delay matching buffers. This issue does not affect your design. Ignore the pre-compile timing estimates in the system timing report for the read postamble enable property. This issue will be fixed in the next version of the DDR and DDR2 SDRAM Illegal Byte Group Placements (Stratix & Stratix GX devices only) The IP Toolbench constraint editor allows you to place byte groups on both top and bottom of a Stratix or Stratix GX device at the same time, which causes an error in the Quartus II software. While you can split a DDR or DDR2 SDRAM interface across both the top and bottom of a Stratix device, some manual editing of the data path is required. Altera Corporation 11

DDR & DDR2 SDRAM Controller Compiler This issues affect designs on Stratix and stratix GX devices that split the interface across the top and bottom. The design does not compile. For more information, contact Altera. This issue will be fixed in a future version of the DDR and DDR2 SDRAM DQS I/O Pin Error (Cyclone Devices Only) Under some circumstances, the timing analysis may show that the design requires a dedicated resynchronization clock. The IP Toolbenchgenerated example top-level design does not automatically support a separate resynchronization clock on Cyclone devices, which causes the following error message: Error: DQS I/O pin <path name>cyclone_ddio_bidir:ddio_bidir[0] ioatom must have a combinational output to the device Error: Can't fit design in device This issue affects Cyclone designs for which IP Toolbench recommends a separate resynchronization clock. The design does not compile. Edit the example top-level design to instantiate a second PLL to provide a resynchronization clock with the IP Toolbench-recommended phase offset and connect this clock to the resynch_clk input of the controller. 12 Altera Corporation

DDR & DDR2 SDRAM Controller Compiler v3.2.0 Issues This issue will be fixed in a future version of the DDR and DDR2 SDRAM Design Assistant Warning Messages The Quartus II Design Assistant generates warning messages when the design does not follow a Design Assistant rule, and generates information messages to provide information regarding a rule. If you enable the Design Assistant for a design containing a DDR or DDR2 SDRAM Controller, during compilation you will see the following messages for each of the following device families, which you can safely disregard. Stratix Devices Medium Clock signal source should not drive registers that are triggered by different clock edges Node: dqs_clk[0](tri-state) External reset should be synchronized using two cascaded registers Node: reset_n Stratix II Devices Medium Clock signal source should not drive registers that are triggered by different clock edges Node: dqs_clk[0](tri-state) Cyclone II Devices Medium Clock signal source should drive only input clock ports Node: ddr_pll_cycloneii:g_cyclonepll_ddr_pll_inst altpll: altpll_component _clk0 Clock signal source should not drive registers that are triggered by different clock edges Node: ddr_pll_cycloneii:g_cyclonepll_ddr_pll_inst altpll:altpll_component _clk0 Altera Corporation 13

DDR & DDR2 SDRAM Controller Compiler Cyclone Devices Medium Clock signal source should drive only input clock ports Node: ddr_pll_cyclone:g_cyclonepll_ddr_pll_inst altpll: altpll_component _clk0 This issue affects all configurations. There is no design impact. No workaround is necessary. This issue may be fixed in the next version of the Quartus II software and the DDR and DDR2 SDRAM SOPC Builder System Generation Fails In the SOPC Builder flow, if you use a dedicated resynchronization clock for the DDR2 SDRAM controller, the SOPC Builder generation fails with the following error message: Error: Test Generator Program for module 'ddr_sdram' did NOT run successfully. This issue affects the DDR2 SDRAM controller when you use the SOPC builder flow and use a dedicated resynchronization clock. SOPC Builder generation fails. 14 Altera Corporation

Contact Information There are two workarounds. You can run the system in a single clock domain. Or locate and change the following line in the generate_ddr_sim_model.pl file in the \lib\sopc_builder\ddr2_sdram_component\ directory: my $number_of_lump_delays = ($rtl_sim_delay / ($clockperiod / 4) + 1); Change it to the following code: my $number_of_lump_delays = floor($rtl_sim_delay / ($clockperiod / 4) + 1); This issue will be fixed in the next version of the DDR and DDR2 SDRAM Contact Information Revision History For more information, contact Altera s mysupport website at www.altera.com/mysupport and click Create New Service Request. Choose the Product Related Request form. Table 1 shows the revision history. Table 1. Revision History Version Date Details of Change 1.1 May 2005 Added issues DDR SDRAM Controller Write Data Slip Errors on page 2 Clock Pin Names Must End In [0] on page 3 Creating Custom Variations In Directories Other Than The Quartus II Project Directory on page 3 DDR or DDR2 SDRAM Controller Version 3.2.0 Cyclone II Devices in a Quartus II v5.1 Project on page 4 SOPC Builder System Generation Fails on page 14 1.0 May 2005 First release of the DDR & DDR2 SDRAM Controller Compiler errata sheet for version 3.2.0. Altera Corporation 15