ALTDQ_DQS2 Megafunction User Guide

Transcription

1 ALTDQ_DQS2 Megafunction ALTDQ_DQS2 Megafunction 101 Innovation Drive San Jose, CA UG Feedback Subscribe

2 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

3 1. About This Megafunction UG This user guide describes the features of the ALTDQ_DQS2 megafunction that you can configure through the MegaWizard interface in the Quartus II software. The ALTDQ_DQS2 megafunction controls the double data rate (DDR) I/O elements (IOEs) for the data (DQ) and data strobe (DQS) signals in Arria V, Cyclone V, and Stratix V devices. A DQ group is composed of one DQS, one optional complementary DQS, and up to 36 configurable DQ I/Os. Features f This user guide assumes that you are familiar with megafunctions and how to create them. If you are unfamiliar with Altera megafunctions or the MegaWizard interface, refer to the Megafunction Overview. The ALTDQ_DQS2 megafunction provides the following features: Access to dynamic on-chip termination (OCT) controls to switch between parallel termination during reads and series termination during writes. High-performance support for DDR interface standards. 4- to 36-bit programmable DQ group widths. Half-rate registers to enable successful data transfers between the I/O registers and the core logic. Access to I/O delay chains to fine-tune delays on the data or strobe signals. Access to hard read FIFO. Access to latency shifter FIFO and data valid FIFO for efficient control of DQS gating and read operations (Arria V and Cyclone V devices only) Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered ALTDQ_DQS2 Megafunction January 2013 Subscribe

4 1 2 Chapter 1: About This Megafunction Device Support Device Support The ALTDQ_DQS2 megafunction supports Arria V, Cyclone V, and Stratix V devices. Resource Utilization and Performance For details about the resource usage and performance of your design, refer to the compilation reports in the Quartus II software. To view the compilation reports in the Quartus II software, follow these steps: 1. On the Processing menu, click Start Compilation to run a full compilation. 2. After compiling the design, on the Processing menu, click Compilation Report. 3. In the Table of Contents browser, expand the Fitter folder by clicking the + icon. 4. Under Fitter, expand Resource section, and select Resource Usage Summary to view the resource usage information. 5. Under Fitter, expand Resource section, and select Resource Utilization by Entity to view the resource utilization information. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

5 2. Parameter Settings UG This section describes the parameter settings for the ALTDQ_DQS2 megafunction. You can instantiate and parameterize the megafunction using either the MegaWizard Plug-In Manager or the ip-generate command through the command-line interface (CLI). f For more information about using the ip-generate command, refer to IP-Generate Command on page A 1. 1 Altera recommends that you configure the megafunction using the MegaWizard Plug-In Manager. Table 2 1. ALTDQ_DQS2 Parameter Settings (Part 1 of 5) General Settings MegaWizard Parameter CLI Parameter Name Legal s Name Legal s (1) Pin width 1 to 36 PIN_WIDTH 1 to 36 Pin type input, output, bidir Extra output-only pins 0 to 36 PIN_TYPE EXTRA_OUTPUT_ WIDTH input,output, bidir 0 to 36 Memory frequency INPUT_FREQ Description This setting specifies the number of data (DQ) pins to make as part of this DQS group. The default value is 9 (9). This setting specifies the direction of the data pins (input, output, or bidirectional). The default value is bidir (bidir). This setting specifies the extra output pins that you need as part of a DQS group. A common use for this setting is to add datamask pins. The default value is 0 (0). This setting specifies the full-rate clock frequency of the incoming DQS group signal from the external device in MHz. The default value is 300 MHz (300) Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered ALTDQ_DQS2 Megafunction January 2013 Subscribe

6 2 2 Chapter 2: Parameter Settings Table 2 1. ALTDQ_DQS2 Parameter Settings (Part 2 of 5) Use DLL Offset Control USE_OFFSET_CTRL true, false Enable hard FIFOs USE_HARD_FIFOS true, false Use Capture Clock to clock the read Side of the Hard VFIFO Enable dual write clocks MegaWizard Parameter Use dynamic configuration scan chains USE_DQSIN_FOR_ VFIFO_READ CLI Parameter Name Legal s Name Legal s (1) true, false DUAL_WRITE_CLOCK true, false USE_DYNAMIC_CONFIG true, false Description This setting enables dynamic control of the DLL offset. Altera recommends using this setting for test purposes only. For DQS data capture calibration, use the D1, D2, D3, and D4 delay chains. This setting enables the hard FIFOs (read FIFO for Stratix V devices and read FIFO, latency shifter FIFO and data valid FIFO for Arria V and Cyclone V devices) as part of the ALTDQ_DQS2 megafunction. Turn on this setting when you use the hard data valid FIFO and when the capture clock is not gated. This setting is available only for Arria V and Cyclone V devices. This setting enables the use of separate output clocks for data and strobe. This setting is disabled by default for Arria V and Cyclone V devices. This setting enables run-time configuration of multiple delay chains, phase shifts, and transfer registers. Requires a correctly formatted bitstream. For more information, refer to DQS Configuration Block Bit Sequence for Stratix V Devices on page 4 5 and DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices on page ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

7 Chapter 2: Parameter Settings 2 3 Table 2 1. ALTDQ_DQS2 Parameter Settings (Part 3 of 5) Output Path Use half-rate output path Use output phase alignment blocks Capture Strobe Capture strobe type Use inverted capture strobe DQS phase shift MegaWizard Parameter HALF_RATE_OUTPUT true, false Single, Differential, Complimentary 0, 45, 90, 135 degrees USE_OUTPUT_PHASE_ ALIGNMENT CAPTURE_STROBE_ TYPE INVERT_CAPTURE_ STROBE CLI Parameter Name Legal s Name Legal s (1) true, false single, differential, complimentary true, false DQS_PHASE_SETTING 0, 1, 2, 3 Description This setting doubles the width of the data bus on the FPGA side and clocks the FPGA side interface using the half-rate clock input. If this setting is enabled, drive the hr_clock_in port with the half-rate clock signal. When enabling hard read FIFO in a Stratix V device, you must set this parameter to true. This setting is enabled by default. This setting enables phase shift on the output path based on the delay settings from the DLL. This setting is disabled by default. This setting specifies the type of capture strobe (DQS signal from the external device). The default value is Single (single). When enabled, this parameter captures data with an inverted capture strobe. Strobe inversion occurs from dqsbusout (an output port from the DQS delay chain block) to the clock input of the DDIO_IN block. This setting is enabled by default. This setting specifies the phase shift value for the DQS delay chain to shift the incoming strobe in the data valid window during read and write operations. The default value is 90 degrees (2). This setting is for Stratix V devices only. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

8 2 4 Chapter 2: Parameter Settings Table 2 1. ALTDQ_DQS2 Parameter Settings (Part 4 of 5) Use capture strobe enable block Treat the capture strobe enable as a half-rate signal DQS enable phase setting Output Strobe MegaWizard Parameter USE_DQS_ENABLE true, false 0, 45, 90, 135 degrees USE_HALF_RATE_DQS_ ENABLE DQS_ENABLE_PHASE_ SETTING true, false 0, 1, 2, 3 Generate output strobe USE_OUTPUT_STROBE true, false Make capture strobe bidirectional Differential/ complimentary output strobe Use reset signal to stop output strobe USE_BIDIR_STROBE true, false DIFFERENTIAL_ OUTPUT_STROBE CLI Parameter Name Legal s Name Legal s (1) USE_OUTPUT_STROBE_ RESET true, false true, false Description This setting enables the capture strobe enable block, which allows control over the preamble state of the capture strobe. This setting is disabled by default. This setting doubles the width of the capture strobe enable bus on the FPGA side and clocks the FPGA side interface using the half-rate clock input. This setting specifies the value of phase shift to shift the full-rate clock signal that drives the capture strobe enable block. The default value is 0 degrees (0). This setting generates an output strobe signal based on the OE signal and the full-rate clock. This setting is enabled by default. This setting enables the bidirectional capture strobe (capture strobe and output strobe is on the same port). This setting is disabled by default. This setting enables either the differential or complimentary output strobe. This setting is disabled by default. This setting stops the unidirectional output strobe using a user-provided reset signal. The core_clock_in and the reset_n_core_clock_in signals are required. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

9 Chapter 2: Parameter Settings 2 5 Table 2 1. ALTDQ_DQS2 Parameter Settings (Part 5 of 5) OCT Source Preamble type Note to Table 2 1: MegaWizard Parameter Output Strobe Enable, Data Write Enable, Dedicated OCT Enable high, low, none OCT_SOURCE 0,1,2 PREAMBLE_TYPE CLI Parameter Name Legal s Name Legal s (1) high, low, none (1) All CLI parameter values are type string, therefore you must enclose the values in double quotes. Description This setting specifies the type of input signal to toggle the OCT control: Output Strobe Enable Uses the output_strobe_ena input as the OCT control signal. Data Write Enable Uses the write_oe_in input as the OCT control signal. Dedicated OCT Enable Adds a oct_ena_in input to the interface, which is used as the OCT control signal. The availability of the Output Strobe Enable, Data Write Enable, and Dedicated OCT Enable are dependent on PIN_TYPE and USE_BIDIR_STROBE parameters. Default value is Data Write Enable. This setting sets the DQS preamble to high (DDR3), low (DDR2, LPDDR2), or none: When you select low and the strobe is bidirectional, the output strobe is held low for the first full rate cycle. When you select high or none, the strobe is driven high for the first full rate cycle. Default value is low. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

10 2 6 Chapter 2: Parameter Settings ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

11 3. Functional Description UG ALTDQ_DQS2 Datapaths This section describes the read and write datapaths and using other megafunctions with the ALTDQ_DQS2 megafunction. DQ and DQS Input Path The DQ and DQS input paths receive the DQ and DQS signals from the external device during read operations. Figure 3 1 shows the input paths where x = 0 to (n-1) and n = the number of DQ pins. Figure 3 1. DQ and DQS Input Paths for Stratix V Devices capture_strobe_ena strobe_ena_clock_in DQS Enable Control IN OUT capture_strobe_in (from DQS pin) (2) PRE D Q DQS Delay Chain DQSBUSOUT DQSIN capture_strobe_out (5) DQS Enable read_data_in[x] (from DQ pin) (1) IN LO read_data_out[x] CLK HI read_data_out[n+x] Notes to Figure 3 1: DDIO_IN (3), (4) (1) For bidirectional DQ, the input of the buffer connects to the read_write_data_io[x] port. (2) For bidirectional DQS, the input of the buffer connects to the strobe_io port. (3) You can use the DDIO_IN block with a soft or hard read FIFO in Stratix V devices. However, you can use this block with only a hard read FIFO in Arria V and Cyclone V devices. (4) When the hard read FIFO block is not present, the DQ and DQS path ends at the DDIO_IN block. For more information about the DQ and DQS input path with a hard read FIFO block, refer to Figure 3 2 and Figure 3 3. (5) Optional inversion occurs from dqsbusout (output port from the DQS delay chain block) to the clock input of the DDIO_IN block. The DQ and DQS input paths in Arria V and Cyclone V devices are the same, except for an additional read FIFO block to implement the second-stage rate conversion DDIO. The high-speed 4 x 8 read FIFO, clocked by the DQS clock, implements the half-rate to full-rate conversion, if necessary Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered ALTDQ_DQS2 Megafunction January 2013 Subscribe

12 3 2 Chapter 3: Functional Description ALTDQ_DQS2 Datapaths Figure 3 2 shows the data input path (when you enable the hard read FIFO) for Arria V, Cyclone V, and Stratix V devices. Figure 3 2. Data Input Path for Arria V, Cyclone V, and Stratix V Devices (1) DATAIN Delay Chain DDIO In FIFO WREN Logic WREN Read FIFO REN FIFO REN Logic DATAOUT[0] DATAOUT[1] DATAOUT[2] DATAOUT[3] HR or FR Clock DQS from DQS Logic Note to Figure 3 2: (1) Figure 3 2 is applicable to Stratix V devices because Stratix V devices support optional hard read FIFO. Table 3 1. DQ and DQS input Path Table 3 1 lists the blocks in the DQ and DQS input paths. Block name DQS enable DQS enable control DQS delay chain Description Represents the AND-gate control on the DQS input that grounds the DQS input strobe when the strobe goes to Hi-Z after a DDR read postamble. The DQS enable block enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change. For more information about the DQS enable block, refer to the Update Enable Circuitry in the External Memory Interfaces chapter in the respective device handbook. Represents the circuitry that controls the DQS enable block. A DQS enable control block controls each DQS enable block. For more information about the DQS enable control block, refer to the DQS Postamble Circuitry in the External Memory Interfaces chapter in the respective device handbook. Represents the delay chains that delay signals. For more information about the DQS delay chain block, refer to DQS Delay Chain in the External Memory Interfaces chapter in the respective device handbook. DQS Logic The DQS input path in Arria V and Cyclone V devices has the following differences from Stratix V and earlier versions of the device families: A data valid FIFO delays the DQS enable path by up to 16 full-rate cycles. During a required calibration process, you can increase the unknown delay, which the data valid FIFO implements, by 1, by pulsing the INC_WR_PTR port. The delay wraps around after 16 increments. The DQS delay chain implements a static non-programmable phase shift of 90. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

13 Chapter 3: Functional Description 3 3 ALTDQ_DQS2 Datapaths Figure 3 3 shows the DQS input path in Arria V and Cyclone V devices. Figure 3 3. DQS Input Path in Arria V and Cyclone V Devices Read FIFO Write Enable capture_strobe_in capture_strobe_ena[0] (2) capture_strobe_ena[1] (2) DDIO Out Data Valid FIFO (1) inc_wr_ptr DQS Enable Control DQS Delay Chain DQS Clock Tree FR Clock strobe_ena_hr_clock_in vfifo_inc_wr_ptr Notes to Figure 3 3: (1) The data valid FIFO is a hard FIFO in Arria V and Cyclone V devices. (2) These ports are 2-bit wide because the DDIO_OUT block is driven by a half-rate clock, allowing you to enable DQS during a half-rate cycle. Capture DDIO to Read FIFO Path The capture DDIO block captures input data (DQ) on the rising and falling edges of the capture clock or strobe (DQS). For Stratix V devices, the capture DDIO block feeds the hard read FIFO or bypasses the hard read FIFO and goes directly to the core. If the capture DDIO block connects directly to the core, the data is transmitted at full rate. For protocols with bidirectional DQS, only an exact number of DQS edge is available for both capturing data in the capture DDIO block and then either in the read FIFO or in the core. The data transfer from the capture DDIO block and the next stage is referred to as zero-cycle transfer. This means that the transfer must happen on the same clock edge. The hard read FIFO always changes the data rate from full-rate to half-rate, so if you choose to use full-rate, then you cannot use the Read FIFO. For Arria V and Cyclone V devices, the capture DDIO block to Read FIFO path is similar, with the following exceptions: The read FIFO must always be used and cannot be bypassed. The read FIFO supports both half-rate and full-rate. For Arria V, Cyclone V, and Stratix V devices, the hard read FIFO implements the functionality of a generic asynchronous FIFO. You can locate the hard read FIFO in a true dual-ported RAM. Data is written to the write side of the DQS clock domain and read from the read side of the core clock domain. For Arria V and Cyclone V devices, the core clock domain can run at half the frequency and implements a full-rate to half-rate transformation. You can use the write enable and read enable signals to control when to write and read data from the read FIFO. The same signal controls the increment of the write and read pointers. For protocols using a bidirectional strobe, the write enable signal is tied to VCC and DQS gating/ungating implements the write enable functionality. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

14 3 4 Chapter 3: Functional Description ALTDQ_DQS2 Datapaths 1 For Arria V and Cyclone V devices, the hard data valid FIFO internally generates the write enable (or gating/ungating) signal, while the hard latency FIFO internally generates the read enable signal. FIFO Control For Arria V and Cyclone V devices, in addition to the read FIFO and the data valid FIFO, the location of the latency shifter FIFO is in each DQS group. The latency shifter FIFO takes in a read-enable command from the core and implements a programmable latency of up to 32 cycles before feeding into the read-enable port of the read FIFO. You can use the output of the data valid FIFO to perform the following tasks: To ungate the DQS logic when a strobe signal is capturing the data. In this case, the write-enable port must always be '1' on the read FIFO. To enable the read FIFO write-enable port when a clock is in use. Figure 3 4 shows the three FIFOs interconnection. Figure 3 4. Data Valid FIFO, Latency Shifter FIFO, and Read FIFO Interconnection Data to Core DOUT DIN Data from DQ Read FIFO (1) REN WREN Latency Shifter FIFO Read Data Enable from Core Data Valid FIFO To DQS Enable Note to Figure 3 4: (1) The read FIFO block is a hard FIFO in Arria V, Cyclone V, and Stratix V devices. The latency shifter FIFO and data valid FIFO are hard FIFO in Arria V and Cyclone V devices. When a read command is sent to the memory device, a read-data-enable token is pushed through the data valid FIFO and the latency shifter FIFO. The data valid FIFO implements a latency equal to the read command to data latency. When the token comes out of the data valid FIFO, the DQS signal is ungated. The latency shifter FIFO then creates enough space between write and read pointers in the read FIFO to ensure that the data read on the read side is correct. If the read FIFO is read at half-rate, the read FIFO also implements a full-rate to half-rate conversion. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

15 Chapter 3: Functional Description 3 5 ALTDQ_DQS2 Datapaths The determination of the correct latencies to implement at each of these FIFOs is important and cannot be done during compilation. When you attempt to implement your own custom memory solution, you must also implement some form of calibration algorithm. f For more information, refer to UniPHY External Memory Interface Debug Toolkit chapter in volume 3 of the External Memory Interface Handbook. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

16 3 6 Chapter 3: Functional Description ALTDQ_DQS2 Datapaths DQ and DQS Output Path The DQ and DQS output path sends the DQ and DQS signal to the external device during write operations. Figure 3 5 shows the output path where n = the number of DQ pins and x = 0 to (n-1). Figure 3 5. DQ and DQS Output Path for Stratix V Devices (1) write_oe_in[x] write_oe_in[2x] write_oe_in[2x+1] hr_clock_in LO HI OUT Half-rate to single-rate output enable registers 0 1 Alignment clock (3) datain dataout Output phase alignment registers 0 1 Write clock (4) D DFF Q write_data_in[x] write_data_in[3n+x] write_data_in[n+x] hr_clock_in HI LO OUT Half-rate to single-rate output registers 0 1 Alignment clock (3) datain dataout Output phase alignment registers 0 1 HI LO OUT DDR output registers Write clock (4) (2) (to DQ pin) write_data_out[x] Series termination control (5) write_data_in[n+x] write_data_in[2n+x] write_data_in[x] hr_clock_in HI LO Q Half-rate to single-rate output registers 0 1 Alignment clock (3) datain dataout Output phase alignment registers 0 1 Notes to Figure 3 5: (1) Figure 3 5 is only applicable for Stratix V devices. For Arria V and Cyclone V DQ and DQS output path, refer to Figure 3 7 on page 3 8. (2) For bidirectional DQ, the output of the buffer connects to the read_write_data_io[x] port. (3) The alignment clock comes from the write-leveling delay chains. For more information, refer to Leveling Circuitry section in the External Memory Interfaces in Stratix V Devices chapter in the Stratix V Device Handbook. (4) The write clock comes from the PLL or the write-leveling delay chains. For more information, refer to Leveling Circuitry section in the External Memory Interfaces in Stratix V Devices chapter in the Stratix V Device Handbook. (5) The series termination control connects to the ALTOCT megafunction. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

17 Chapter 3: Functional Description 3 7 ALTDQ_DQS2 Datapaths Figure 3 6 shows the DQ and DQS output path for additional DQ pins usage, where y = 0 to (m-1) and m= the number of DQ pins. Figure 3 6. DQ and DQS Output Path (for Additional DQ Pins Usage) for Stratix V Devices VCC extra_write_data_in[y] extra_write_data_in[3m+y] extra_write_data_in[2m+y] hr_clock_in HI LO OUT Half-rate to single-rate output enable registers 0 1 Alignment clock (1) datain dataout Output phase alignment registers 0 1 HI OUT LO DDR output registers Write clock (2) extra_write_data_out[y] (to DQ pin) extra_write_data_in[m+y] extra_write_data_in[y] Notes to Figure 3 6: hr_clock_in HI LO datain dataout (1) The alignment clock comes from the write-leveling delay chains. (2) The write clock comes from the PLL or the write-leveling delay chains. OUT Half-rate to single-rate output registers 0 1 Alignment clock (1) Output phase alignment registers 0 1 Table 3 2 lists the blocks in the DQ/DQS output path. Table 3 2. DQ/DQS Output Path for Stratix V Devices Block name Half-rate to single-rate output enable registers Output phase alignment registers DDR output registers Description Represents a group of registers that convert half-rate data to single-rate data. Represents the circuitry required to phase shift the DQ-output signals. Use this block for write-leveling purposes in DDR3 SDRAM interfaces. Represents the DDIO registers that transfer DDR signals from the core to the DQ/DQS pins. f For more information about how the input and output paths are mapped to the device IOEs, refer to I/O Element Registers in the External Memory Interfaces chapter in the respective device handbook. The data output path for Arria V and Cyclone V families is similar to the output paths for Stratix V and earlier families, except for the output phase alignment registers. These registers are not available in Arria V and Cyclone V devices and do not support leveled interfaces. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

18 3 8 Chapter 3: Functional Description ALTDQ_DQS2 Datapaths Figure 3 7 shows the DQ and DQS output path for Arria V and Cyclone V devices. Figure 3 7. DQ and DQS Output Path for Arria V and Cyclone V Devices OCT from DQS Logic OE from Output Enable Path DATAOUT[0] DATAOUT[2] DDIO Out DDIO Out DATAOUT DATAOUT[1] DATAOUT[3] DDIO Out CLK_HR CLK_FR You must connect the ALTDQ_DQS2 megafunction to the ALTOCT, ALTDLL, and ALTERA_PLL megafunctions to utilize their features. Table 3 3 describes how to use the ALTOCT, ALTDLL, and ALTERA_PLL megafunctions with the ALTDQ_DQS2 megafunction: Table 3 3. Using the ALTDLL, ALTERA_PLL, and ALTOCT Megafunctions with the ALTDQ_DQS2 Megafunction (Part 1 of 2) Megafunction ALTDLL Description The ALTDLL megafunction instantiates a delay-locked loop (DLL) circuit in your design. The DLL circuit represents the specialized phase-shift reference circuit for calibrating the delay settings of the DQS delay chains, allowing the delay chains to compensate for PVT variations. The DLL uses a reference clock at the same frequency as the input DQS signal to compute the amount of delay required at each DQS pin on the FPGA to perform the phase-shift. Use of the DLL Offset Control is recommended for test purposes only. For DQS data capture calibration, use the D1, D2, D3, and D4 delay chains. For more information about DLL in Arria V, Cyclone V, and Stratix V devices, refer to the DQS Phase-Shift Circuitry section in the External Memory Interfaces chapter in the respective device handbook. For more information about the ALTDLL megafunction, refer to the ALTDLL and ALTDQ_DQS Megafunction. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

19 Chapter 3: Functional Description 3 9 ALTDQ_DQS2 Datapaths Table 3 3. Using the ALTDLL, ALTERA_PLL, and ALTOCT Megafunctions with the ALTDQ_DQS2 Megafunction (Part 2 of 2) Megafunction ALTERA_PLL ALTOCT Description The ALTERA_PLL megafunction instantiates a phase-locked loop (PLL) circuit in your design. The PLL generates the related clock signals that are used by the IOEs. For more information about the Arria V, Cyclone V, and Stratix V PLL, refer to the Clock Networks and PLLs chapter in the respective device handbook. For more information about the ALTERA_PLL megafunction, refer to the Altera Phase-Locked Loop (ALTERA_PLL) Megafunction. The ALTOCT megafunction instantiates an on-chip termination (OCT) calibration block in your design. The block provides dynamic OCT control for I/O impedance matching and termination. The OCT maintains signal quality, saves board space, and reduces external component costs. For more information about dynamic OCT control, refer to the Dynamic On-Chip Termination Control section in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook. For more information about the ALTOCT megafunction, refer to the Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction. For more information about instantiating these megafunctions, refer to Instantiating Megafunctions on page 5 1. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

20 3 10 Chapter 3: Functional Description ALTDQ_DQS2 Ports ALTDQ_DQS2 Ports This section describes the ports of the ALTDQ_DQS2 megafunction. Figure 3 8 shows the data strobe, data, termination control, PLL, DLL, hard FIFO, and dynamic configuration ports of the megafunction. Figure 3 8. ALTDQ_DQS2 Block Diagram config_clock_in (6), (7) config_data_in (6), (7) config_dqs_ena (6), (7) config_dqs_io_ena (6), (7) config_update (6), (7) core_clock_in (7), (10) fr_clock_in (4), (7) hr_clock_in (4), (7) lfifo_reset_n (5), (9) lfifo_rden (5), (8) reset_n_core_clock_in (1), (7) rfifo_reset_n (5), (9) strobe_ena_hr_clock_in (1), (7) vfifo_reset_n (5), (9) write_strobe_clock_in (1), (7) dll_delayctrl_in[] (4), (7) capture_strobe_ena[] (1), (8) output_strobe_ena[] (1), (7) oct_ena_in[] (1), (7) parallelterminationcontrol_in[] (3), (7) seriesterminationcontrol_in[] (3), (7) write_oe_in[] (2), (7) write_data_in[] (2), (7) config_io_ena[] (6), (7) lfifo_rdata_en[] (5), (9) lfifo_rdata_en_full[] (5), (9) lfifo_rd_latency[] (5), (9) vfifo_qvld[] (5), (9) vfifo_inc_wr_ptr[] (5), (9) capture_strobe_in (1), (7) capture_strobe_n_in (1), (7) extra_write_data_in[] (2), (7) read_data_in[] (2), (7) config_extra_io_ena[] (6), (7) ALTDQ_DQS2 capture_strobe_out (1), (7) strobe_io (1), (7) read_data_out[] (2), (7) read_write_data_io[] (2), (7) lfifo_rdata_valid (5), (9) output_strobe_n_out (1), (7) output_strobe_out (1), (7) extra_write_data_out[] (2), (7) write_data_out[] (2), (7) strobe_n_io (1), (7) Notes to Figure 3 8: (1) This is a data strobe port. For more information about the port, refer to Table 3 4 on page (2) This is a data port. For more information about the port, refer to Table 3 5 on page (3) This is a termination control port. For more information about the port, refer to Table 3 6 on page (4) This is a PLL/DLL port. For more information about the port, refer to Table 3 7 on page (5) This is a hard FIFO port. For more information about the port, refer to Table 3 8 on page (6) This is a dynamic configuration port. For more information about the port, refer to Table 3 9 on page (7) This port is supported in Arria V, Cyclone V, and Stratix V devices. (8) This port is only supported in Stratix V devices. (9) This port is only supported in Arria V and Cyclone V devices. (10) This signal is used for QDRII. This clock, unlike other clocks, can be held at zero during initialization, which is a requirement for QDRII. Use the core clock signal for internal purposes. In a half-rate application, the core clock signal is unconnected. In a full-rate application, you must connect the core clock signal to the full-rate clock. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

21 Chapter 3: Functional Description 3 11 ALTDQ_DQS2 Ports Table 3 4 lists the ALTDQ_DQS2 megafunction data strobe ports. Table 3 4. ALTDQ_DQS2 Megafunction Data Strobe Ports Port Name Type Width Description capture_strobe_ena Input 1 capture_strobe_n_in Input 1 capture_strobe_in Input 1 capture_strobe_out Output 1 output_strobe_ena oct_ena_in Input Input 2 = half-rate 1 = full-rate 2 = half-rate 1 = full-rate reset_n_core_clock_in Input 1 write_strobe_clock_in Input 1 Controls the DQS enable control block by acting as the gating signal for signals coming from the input registers (capture_strobe_in) to reach the DQS delay chain block. Receives the negative polarity clock signal from the external device. For example, a DQSn signal from the external memory. This port is available when the capture strobe type is set to differential or complimentary. Receives the clock signal from the external device, for example, a DQS signal from the external memory. Sends the delayed clock signal to the core. For example, a delayed DQS signal from the DQS delay chain. The gating signal for the output_strobe_out port. Controls the dynamic on-chip-termination signal for all data and strobe ports. Asynchronous reset used in QDRII-like interfaces to reset the write strobe. Receives the clock signal from the core. For example, a DQS signal from the core. Clocks the DDIO that generates the output strobe signal. strobe_ena_hr_clock_in Input 1 Receives the clock signal from the clock pin or the PLL to clock the DQS enable control block. Also a half-rate signal that, after going through the DQS_ENABLE_CTRL input, controls the gating of the input strobe. strobe_io Bidirectional 1 Sends and receives the bidirectional clock signal. strobe_n_io Bidirectional 1 output_strobe_out Output 1 output_strobe_n_out Output 1 Sends and receives the negative polarity clock signal for differential or complimentary strobe configuration. Sends clock signal to the external device. For example, a DQS signal to the external memory. Sends the negative polarity clock signal to the external device (For example, DQSn signal to the external memory). This port is available when you set the output strobe type to differential or complimentary. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

22 3 12 Chapter 3: Functional Description ALTDQ_DQS2 Ports Table 3 5 lists the ALTDQ_DQS2 megafunction data ports where n= number of DQ pins, m= number of additional output-only DQ pins, x = 0 to (n-1), and y= 0 to (m-1). Table 3 5. ALTDQ_DQS2 Megafunction Data Ports (Part 1 of 2) Port Name Type Width (1) Description extra_write_data_in[] Input 2m = full-rate 4m = half-rate extra_write_data_out[] Output m read_data_in[] Input n read_data_out[] Output 2n = full-rate 4n = half-rate read_write_data_io[] Bidirectional n write_data_in[] Input 2n = full-rate 4n = half-rate write_data_out[] Output n Receives data signal from the core. This port connects to the input port of the half-rate data to single-rate data output registers block (Figure 3 6 on page 3 7). In full-rate mode, only the extra_write_data_in[y] and extra_write_data_in[m+y] ports are used. Sends data to the external device. This port connects to the output port of the output buffer (Figure 3 6 on page 3 7). Receives data from the external device. This port connects to the input port of the input buffer located between the DQ pin and the DDR input registers block. This is an input-only DQ port that receives data from the external device (Figure 3 1 on page 3 1). Sends the captured data from the external device to the core. This port connects to the output port of the DDR input register block (Figure 3 1 on page 3 1). The read_data_out[x] port outputs the positive-edge triggered data, and the read_data_out[n+x] port outputs the negative-edge triggered data. Receives and sends data between the core and the external device. You must assign the bidirectional DQ port with the output termination and input termination assignments. Receives DDR data signal from the core to be sent out to the external device. For example, data to be written to the external memory during write operation. This port connects to the input port of the half-rate data to single-rate data output registers block (Figure 3 5 on page 3 6). In full-rate mode, the megafunction uses only the write_data_in[x] and write_data_in[n+x] ports. Sends the DDR data signal to the external device. For example, data to be written to the external memory during write operation. This port connects to the output port of the output buffer located between the DDR output registers block and the DQ-out pin (Figure 3 5 on page 3 6). ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

23 Chapter 3: Functional Description 3 13 ALTDQ_DQS2 Ports Table 3 5. ALTDQ_DQS2 Megafunction Data Ports (Part 2 of 2) write_oe_in[] Note to Table 3 5: Port Name Type Width (1) Description Input n = full-rate 2n = half-rate (1) The port width applies to full-rate mode, unless otherwise specified. Receives the gating signal from the core to control the output buffer. For example, gating control when writing data to the external memory during write operation. This port connects to the input port of the half-rate data to single-rate data output-enable registers block (Figure 3 5 on page 3 6). In full-rate mode, the megafunction uses only the write_oe_in[x] port. f To understand how these ports connect to the IOEs, refer to I/O Elements in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook. Table 3 6 lists the terminal control ports. Table 3 6. ALTDQ_DQS2 Megafunction Temination Control Ports Port name Type Width Description paralleltermination control_in[] Input 16 seriesterminationcontrol_in[] Input 16 Controls the calibrated parallel termination ports of the input buffers. You must connect this port to the parallelterminationcontrol[15:0] port of the ALTOCT megafunction. Ensure that the termination block located in the ALTOCT instance is assigned with the termination control block assignment. Controls the calibrated series termination ports of the output buffers. You must connect this port to the seriesterminationcontrol[15:0] port of the ALTOCT megafunction. Ensure that the termination block located in the ALTOCT instance is assigned with the termination control block assignment. f For more information about dynamic OCT control in Stratix V devices, refer to the DC and Switching Characteristics for Stratix V Devices chapter in volume 3 of the Stratix V Device Handbook. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

24 3 14 Chapter 3: Functional Description ALTDQ_DQS2 Ports Table 3 7. PLL and DLL Ports Table 3 7 lists the PLL and DLL ports. Port name Type Width Description dll_delayctrl_in[] Input 7 fr_clock_in Input 1 hr_clock_in Input 1 Receives the 7-bit delay settings from the dll_delayctrlout port of the ALTDLL megafunction instance. This 7-bit signal controls delay through the DQS delay chains. Compilation error occurs if this port is not connected to a DLL. Receives the full-rate clock signal from a clock pin, or the PLL clock output port. Receives the half-rate clock signal from a clock pin, or the PLL clock output port. f f For more information about DLL in Stratix V device, refer to Delay-Locked Loop in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook. For more information about PLL in Stratix V devices, refer to PLL Specifications in DC and Switching Characteristics for Stratix V Devices chapter of the Stratix V Device Handbook. Table 3 8. Hard FIFO Ports Table 3 8 lists the signals for Arria V and Cyclone V devices. Ports Type Width Description lfifo_rdata_en Input 2 The read enable signal indicates that read data is expected at the latency provided by the latency shifter FIFO. The delayed signal gets passed to the read FIFO read-enable port. lfifo_rdata_en_full Input 2 Data input to the latency shifter FIFO. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst. This token is delayed by a variable number of integer cycles inside the latency shifter FIFO and used to feed the read enable signal of the read FIFO. lfifo_reset_n Input 1 Active low reset to the latency shifter FIFO lfifo_rd_latency[] Input 5 vfifo_qvld Input 2 The number of cycles to delay data inputs feeding the latency shifter FIFO. A maximum of 31 cycles is supported. Data input to the data valid FIFO. This signal is the full read enable token generated by user logic and is asserted for the length of the desired read burst. This signal is driven by the same user logic that drives the lfifo_rdata_en_full signal. vfifo_inc_wr_ptr Input 2 Increments the latency implemented by the data valid FIFO by one cycle. vfifo_reset_n Input 1 Active low reset to the data valid FIFO rfifo_reset_n Input 1 Active low reset to the read FIFO lfifo_rdata_valid Output 1 Signals that the data on read_data_out signal is valid ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

25 Chapter 3: Functional Description 3 15 ALTDQ_DQS2 Ports The I/O and DQS configuration blocks represent a set of serial-to-parallel shift registers that dynamically changes the settings of various device configuration bits. The I/O and DQS configuration blocks shift a serial configuration data stream into the shift registers, and then load the data stream into the configuration registers. The shift registers power-up low. Every I/O pin contains an I/O configuration block. Every DQS group contains a DQS configuration block and an I/O configuration block. Table 3 9 lists the dynamic configuration ports where n= number of DQ pins and m= number of additional DQ pins. Table 3 9. ALTDQ_DQS2 Megafunction Dynamic Configuration Ports Port name Type Width Description config_clock_in (1) Input 1 config_data (1) Input 1 config_io_ena[] (2) Input n config_dqs_io_ena (2) Input 1 config_dqs_ena (2) Input 1 config_update (1) Input 1 config_data_in Input 1 config_extra_io_ena[] Input m Receives the clock signal to clock all dynamic configuration blocks. You can connect this port to a clock pin, or the PLL clock output port. This is the clock signal. All other input signals must be treated as synchronous to this clock. The 1-bit serial input through which data is scanned into the calibration blocks. It is common to all configuration blocks, but it will only be scanned into calibrations blocks whose enable input is asserted. An input port that controls the enable input on the DQ I/O configurations. Receives the clock enable signal for the I/O configuration block. An input port that controls the enable input on the DQS I/O configurations. Receives the clock enable signal for the DQS I/O configuration block. An input port that controls the enable input on the DQS logic. Receives the clock enable signal for the DQS configuration block. Receives the signal to load the bits from the serial-to-parallel shift registers to the configuration registers. After scanning all the bits into the desired scan chain blocks, the bits can be copied at once into the configuration register by asserting the config_update signal for one clock cycle. Receives the serial configuration data stream that shifts into the serial-to-parallel shift registers. Receives the clock enable signal for the additional I/O configuration block. Notes to Table 3 9: (1) The ALTDQ_DQS2 dynamic configuration interface consists of these input ports. (2) For more information, refer to Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction on page 4 1. f For more information about the dynamic configuration blocks in Stratix V device, refer to I/O Configuration Block and DQS Configuration Block in the External Memory Interfaces in Stratix V Devices chapter of the Stratix V Device Handbook. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

26 3 16 Chapter 3: Functional Description ALTDQ_DQS2 Ports ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

27 4. Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction UG Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction When static timing closure is challenging (for example, high frequency, high board trace skew, and high timing uncertainty), dynamically reconfiguring the ALTDQ_DQS2 megafunction may provide additional timing margin. Arria V, Cyclone V, and Stratix V devices contain reconfigurable logic, allowing you to adjust the delay of several datapaths at runtime. The I/O configuration block and the DQS configuration block are shift registers that you can use to dynamically change the settings of various device configuration bits. The shift registers are configured with the rest of the device when the Programmer Object File (.pof). In dynamic mode, you can override the static values at runtime with a scan chain. You can reconfigure the I/Os by turning on the Use dynamic configuration scan chains option. Figure 4 1 shows the Use dynamic configuration scan chains option. Figure 4 1. Use Dynamic Configuration Scan Chains Option 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered ALTDQ_DQS2 Megafunction January 2013 Subscribe

28 4 2 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Figure 4 2. Reconfiguration Scan Chain Figure 4 2 shows the dynamic reconfiguration scan chain implementation. config_data DQ0 din update enable clk DQ1 din update enable clk DQS din update enable clk config_clock_in config_update config_io_ena[0] config_io_ena[1] config_dqs_ena Each I/O contains a scan chain block. The DQS logic also contains its own scan chain block. You can use I/O scan chain blocks to configure DQ and DQS I/O configuration registers (for example, delay chain) and you can use the DQS logic scan chain to configure DQS logic configuration (for example, DQS postamble phase). You can serially scan configuration bits into each scan chain block with the following operating sequence: The ALTDQ_DQS2 dynamic configuration interface is made of four input ports: config_clock_in This is the clock signal. All other input signals must be treated as synchronous to this clock. The typical frequency is 50 MHz. config_data This is the 1-bit serial input through which data is scanned into the calibration blocks. This is common to all configuration blocks, but it will only be scanned into calibrations blocks whose enable input is asserted. config_enable In a generic ALTDQ_DQS2 IP, the following three config_enable inputs are available: config_io_ena[] Controls the enable input on the DQ I/Os config_dqs_io_ena[] Controls the enable input on the DQS I/Os config_dqs_ena[] Controls the enable input on the DQS logic 1 Each of these inputs is wide to control all the scan chain blocks instantiated in the ALTDQ_DQS2 megafunction. In a general application, you must assert only one enable input at a time to scan the desired data in the corresponding scan chain block. The enable input must be held high for the entire duration of the scanning process. All other inputs must be held at 0. config_update After scanning all the bits into the desired scan chain blocks, copy them into the configuration register by asserting the config_update signal for one clock cycle. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

29 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction I/O Configuration Block Bit Sequence for Stratix V Devices Table 4 1 lists the I/O configuration block bit sequence, description, and settings for Stratix V devices. Table 4 1. I/O Configuration Block Bit Sequence for Stratix V Devices (Part 1 of 2) Bit Bit Name Description 5..0 padtoinputregisterdelaysetting padtoinputregisterrisefalldelaysetting outputdelaysetting1 Connects to the delayctrlin port of the D1 delay chain to control the first I/O buffer-to-input register delay chain (D1). Sets to tune the DQ delay (read calibration) for DDR applications. For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Connects to the delayctrlin port of the second D1 delay chain to control the second pad-to-input register delay chain (D1). For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Connects to the delayctrlin port of the D5 delay chain to control the output register-to-i/o buffer delay chain (D5) in the output path and output enable paths. This delay is for write calibration for DDR application. For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Legend in Figure 4 3 Default (Binary) A B C Min. intrinsic delay intrinsic delay intrinsic delay Max ps + intrinsic delay ps + intrinsic delay ps + intrinsic delay Inc ps 12.5 ps 12.5 ps Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 3 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

30 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 1. I/O Configuration Block Bit Sequence for Stratix V Devices (Part 2 of 2) outputdelaysetting Bit Bit Name Description inputclkndelaysetting inputclkdelaysetting dutycycledelaymode dutycycledelaysetting Connects to the delayctrlin port of the D6 delay chain to control the output register-to-i/o buffer delay chain (D6) in the output path and output enable paths. This delay is for write calibration for DDR application. For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Unconfigurable bits. Always set bits to its default value. Legend in Figure 4 3 Default (Binary) D Min. intrinsic delay Max ps + intrinsic delay Inc ps Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

31 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction DQS Configuration Block Bit Sequence for Stratix V Devices Table 4 1 lists the DQS configuration block bit sequence, description, and settings for Stratix V devices. Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 1 of 8) Bit Bit Name Description 5..0 dqsbusoutdelaysetting dqsbusoutdelaysetting2 Connects to the delayctrlin port of the first D4 delay chain. Controls the first D4 delay chain in DQS delay chain path (after the DQS delay chain). This is the delay tuning of the DQS signal feeding into the DQS bus. For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Connects to the delayctrlin port of the second D4 delay chain. Controls the second D4 delay chain in DQS delay chain path (after the first D4 delay chain). This is the delay tuning of the DQS signal feeding into the DQS Bus. For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Legend in Figure 4 3 Default (Binary) E F Min intrinsic delay intrinsic delay Max ps + intrinsic delay ps + intrinsic delay Inc. Unit 12.5 ps 12.5 ps Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 5 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

32 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 2 of 8) octdelaysetting octdelaysetting Bit Bit Name Description addrphasesetting addrpowerdown addrphaseinvert dqsoutputphasesetting 30 dqsoutputpowerdown Connects to the delayctrlin port of the D5 OCT delay chain. Controls the dynamic OCT output register-to-i/o buffer delay chain (D5). For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Connects to the delayctrlin port of the D6 OCT delay chain. Controls the dynamic OCT output register-to-i/o buffer delay chain (D6). For delay values, refer to the Programmable IOE Delay section in the Stratix V Device Datasheet. Unconfigurable bits. Always set bits to its default value. Connects to the phasectrlin port of the clock phase select (in the DQS output path) to select between phase shifts of 0, 45, 90, and 135. Use this bit to level the DQS write output. Unconfigurable bits. Legend in Figure 4 3 Default (Binary) G H intrinsic delay intrinsic delay ps + intrinsic delay ps + intrinsic delay 12.5 ps 12.5 ps 0100 I 00 Min 00 = 0 01 = = = 135 Max Always set bits to its default value. 1 Inc. Unit 4 6 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

33 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 3 of 8) 31 dqsoutputphaseinvert dqoutputphasesetting dqoutputpowerdown 36 dqoutputphaseinvert Bit Bit Name Description resyncinputphasesetting resyncinputpowerdown resyncinputphaseinvert Connects to the phaseinvertctrl port of the clock phase select (in the DQS output path) to select between the non-inverted and inverted output. This setting allows the phase output from the delay chain to be inverted to gain additional phases. Connects to the phasectrlin port of the clock phase select (in the DQ output path) to select between phase shifts of 0, 45, 90, and 135. DQ leveling clock select. Use this bit to level the DQ write output. Unconfigurable bits. Always set bits to its default value. Connects to the phaseinvertctrl port of the clock phase select (in the DQ output path) to select between the non-inverted and inverted output. This setting allows the phase output from the delay chain to be inverted to gain additional phases. Unconfigurable bits. Legend in Figure 4 3 Default (Binary) J 0 K 00 0 = bypass 1 = enable 00 = 0 01 = = = L 0 Min 0 = bypass 1 = enable Max Always set bits to its default value Inc. Unit Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 7 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

34 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 4 of 8) Bit Bit Name Description postamblephasesetting postamblepowerdown 45 postamblephaseinvert Connects to the phasectrlin port of the clock phase select (for the DQS enable control block) to select between phase shifts of 0, 45, 90, and 135. Use this clock phase select block to level the postamble (dqsenablein signal at the DQS enable control block). Unconfigurable bits. Always set bits to its default value. Connects to the phaseinvertctrl port of the clock phase select (for the DQS enable control block) to select between the non-inverted and inverted output. Use this clock phase select block to level the postamble (dqsenablein signal at the DQS enable control block). This setting allows the phase output from the delay chain to be inverted to gain additional phases. Legend in Figure 4 3 Default (Binary) M = 0 01 = = = N 0 Min 0 = bypass 1 = enable Max Inc. Unit 4 8 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

35 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 5 of 8) Bit Bit Name Description dqs2xoutputphasesetting dqs2xoutputpowerdown dqs2xoutputphaseinvert dq2xoutputphasesetting dq2xoutputpowerdown dq2xoutputphaseinvert ck2xoutputphasesetting] ck2xoutputpowerdown ck2xoutputphaseinvert dqoutputzerophasesetting postamblezerophasesetting postamblepowerdown dividerioehratephaseinvert dividerphaseinvert enaoctcycledelaysetting Unconfigurable bits. Always set bits to its default value. Connects to the enaoutputcycledelay port of the output alignment block (in the dynamic OCT control path) to allow additional registers to be used. Use this bit to adjust the phase of the write-leveled OCT or output data signal. Legend in Figure 4 3 Default (Binary) 0010_0000_1000_1000_010 0 O 010 Min Max 000: Not supported 001: Not supported 010: No delay 011: 1 cycle delay 100: 2 cycle delay 101: 3 cycle delay 110: Not supported 111: Not supported Inc. Unit Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 9 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

36 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 6 of 8) Bit Bit Name Description 69 enaoctphasetransferreg dqsdisablendelaysetting dqsenabledelaysetting Connects to the enaphasetransferreg port of the output alignment block (in the dynamic OCT control path) to allow an additional negative edge-triggered register to be added to the OCT, output data, or output enable path to satisfy the setup or hold time requirement for the phase transfer. Connects to the delayctrlin port of the T11 delay chain (located between the dqsenableout port of the DQS enable control block and the dqsdisablen port of the DQS delay chain). This is to align post-amble signal in terms of DQS signal by selecting different delays. Connects to the delayctrlin port of the T11 delay chain (located between the dqsenableout port of the DQS enable control block and the dqsenable port of the DQS delay chain). This is to align post-amble signal in terms of DQS signal by selecting different delays. Legend in Figure 4 3 Default (Binary) P 0 Q R Min 0 = bypass 1 = enable intrinsic delay intrinsic delay Max 3.2 ns + intrinsic delay 3.2 ns + intrinsic delay Inc. Unit 12.5 ps 12.5 ps 4 10 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

37 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 7 of 8) Bit Bit Name Description 86 enadqsenablephasetransferreg dqsinputphasesetting 89 enadqsphasetransferreg 90 enaoutputphasetransferreg Connects to the enaphasetransferreg port of the DQS enable control block to allow an additional negative edge-triggered register to be added to the DQS enable control path to satisfy the setup or hold time requirement for the phase transfer. Connects to the phasectrlin port of the DQS delay chain block. To control the phase selection for the DQS delay chain. The frequency range that this works at is 300 MHz to 800 MHz. Connects to the enaphasetransferreg port of the output alignment block (in the DQS output path and OE path) to allow an additional negative edge-triggered register to be used. Connects to the enaphasetransferreg port of the output alignment block (in the DQ output path and OE path) to allow an additional negative edge-triggered register to be added to the output data or output enable path to satisfy the setup or hold time requirement for the phase transfer. Legend in Figure 4 3 Default (Binary) S 0 T 00 U 0 V 0 Min 0 = bypass 1 = enable 00 = 0 01 = = = = bypass 1 = enable 0 = bypass 1 = enable Max Inc. Unit Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 11 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

38 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 2. DQS Configuration Block Bit Sequence for Stratix V Devices (Part 8 of 8) Bit Bit Name Description enadqscycledelaysetting enaoutputcycledelaysetting enainputcycledelaysetting enainputphasetransferreg Connects to the enaoutputcycledelay port of the output alignment block (in the DQS output path and OE path) to allow additional registers to be enabled in the output alignment block of the output data or output enable path of a DQS I/O. This is normally used to adjust the phase of the write-leveled OCT or output data signal. Connects to the enaoutputcycledelay port of the output alignment block (in the DQ output path and OE path) to allow additional registers to be enabled in the output alignment block of the output data or output enable path of a DQ I/O. Use this bit to adjust the phase of the write-leveled OCT or output data signal. Unconfigurable bits. Always set bits to its default value. Legend in Figure 4 3 Default (Binary) W 010 X 010 Min Max 000: Not supported 001: Not supported 010: No delay 011: 1 cycle delay 100: 2 cycle delay 101: 3 cycle delay 110: Not supported 111: Not supported 000: Not supported 001: Not supported 010: No delay 011: 1 cycle delay 100: 2 cycle delay 101: 3 cycle delay 110: Not supported 111: Not supported Inc. Unit Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

39 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 13 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Figure 4 3. I/O and DQS Delay Chains for Stratix V Devices (1), (2) X V Negative Edge Write Data Positive Edge Write Data Clock Phase Select (0 Degree) Output Alignment Output Alignment 0 1 D5 Delay Chain D6 Delay Chain D6 OE Delay Chain DQ D6 OCT Delay Chain Output Enable Signal X V D5 OE Delay Chain D5 OCT Delay Chain K L Output Alignment Clock Phase Select O P Positive Edge Read Data D3 Delay Chain D2 Delay Chain D1 Delay Chain B D1 Delay Chain A DQ Clock Signal from Core Leveling Delay Chain OCT Control Signal Clock Phase Select Output Alignment Negative Edge Read Data D4 Delay Chain F D4 Delay Chain E T DQS Delay Chain To dqsenable Port To dqsdisablen Port R DQS T11 Delay Chain T11 Delay Chain Q From dqsenableout Port DQS Enable Control S To levelingclk Port To zerophaseclk Port M N Clock Phase Select Clock Phase Select (0 Degree) I J Output Enable Signal Negative Edge Write Data Clock Phase Select (0 Degree) Positive Edge Write Data Output Alignment W Output Alignment W U Output Alignment U 0 1 C D5 Delay Chain D D6 Delay Chain D5 OE Delay Chain D6 OE Delay Chain DQS D5 OCT Delay Chain D6 OCT Delay Chain G H Notes to Figure 4 3: (1) Use the combination of D1, D2, D3, and D4 delay chains for calibration. Use D1, D2, and D3 to delay DQ, and D4 delay chain to delay DQS. D5 and D6 delay chains are the output delay chains. (2) The D2 and D3 delay chains are static input delay chains. You can only set the settings in the Quartus II Settings File (.qsf) or the Fitter sets the settings automatically based on the timing constraints. You cannot dynamically set the settings. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

40 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices Table 4 3 lists the I/O configuration block bit sequence, description, and settings for Arria V and Cyclone V devices. Table 4 3. I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices (Part 1 of 3) Bit External Bit Name Description 4..0 padtoinputregisterdelaysetting 9..5 outputenabledelaysetting Connects to the delayctrlin port of the D1 delay chain. Controls the I/O buffer-to-input register delay chain (D1). Tunes the DQ delay (read calibration) for DDR applications. For delay values, refer to the Programmable IOE Delay section in the Arria V Device Datasheet. For delay values, refer to the Programmable IOE Delay section in the Cyclone V Device Datasheet. Connects to the delayctrlin port of the D5 delay chain. Controls the output register-to-i/o buffer delay chain (D5) in the output enable paths. This delay is used for write calibration for DDR application. For delay values, refer to the Programmable IOE Delay section in the Arria V Device Datasheet. For delay values, refer to the Programmable IOE Delay section in the Cyclone V Device Datasheet. Legend in Figure 4 4 Default (Binary) A B Min. intrinsic delay intrinsic delay Max. 775 ps + intrinsic delay 775 ps + intrinsic delay Inc. 25 ps 25 ps 4 14 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

41 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction Table 4 3. I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices (Part 2 of 3) Bit External Bit Name Description outputregdelaysetting readfifomode readfiforeadclockselect Connects to the delayctrlin port of the D5 delay chain. Controls the output register-to-io Buffer delay chain (D5) in the output path paths. This delay is used for write calibration for DDR application. For delay values, refer to the Programmable IOE Delay section in the Arria V Device Datasheet. For delay values, refer to the Programmable IOE Delay section in the Cyclone V Device Datasheet. Connects to the dynfifomode port of input register read FIFO block. The read FIFO can be configured as a read FIFO or a Unified SerDes Block. Connects to the clksel port of the read FIFO clock select block. This controls the read FIFO Read clock source Select. Legend in Figure 4 4 Default (Binary) C D 000 E 00 Min. intrinsic delay Max. 775 ps + intrinsic delay Inc. 25 ps 000: Half-rate Read FIFO Mode 001: Full-rate Read FIFO Mode 010: Deserializer Bit Slip Mode 011: Deserializer with Input from Bit Slip 100: Deserializer with Input from I/O 101: Serializer mode 110: Not supported 111: Not supported 00: Select Core CLKIN1 01: Select DQS_CLK (PHY_CLK) 10: Select SEQ_HR_CLK (PHY_CLK) 11: Select VCC (Disabled) Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 15 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

42 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 3. I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices (Part 3 of 3) Bit External Bit Name Description 20 outputhalfratebypass Not mapped to any port Sets the multiplexer in the output enable and output data path logic to dynamically bypass the half-rate to full-rate DDIO. Used only with the hard PHY. Unconfigurable bits. Always set bits to its default value. Legend in Figure 4 4 DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Default (Binary) F 0 Min. Max. 0: Engage Half-Rate Register 1: Bypass Half-Rate Register 0000 Table 4 4 lists the DQS configuration block bit sequence, description, and settings for Arria V and Cyclone V devices. Table 4 4. DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices (Part 1 of 3) Bit External Bit Name Description 4..0 dqsenableungatingdelaysetting 9..5 dqsenablegatingdelaysetting Connects to the delayctrlin port of postamble T11 delay chain (ungated). Aligns the postamble signal in terms of DQS signal by selecting different delays. Connects to the delayctrlin port of the postamble T11 delay chain (gated). Aligns the postamble signal in terms of DQS signal by selecting different delays. Legend in Figure 4 4 Default (Binary) G H Min. intrinsic delay intrinsic delay Max. 775 ps + intrinsic delay 775 ps + intrinsic delay Inc. Inc. 25 ps 25 ps 4 16 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

43 January 2013 Altera Corporation ALTDQ_DQS2 Megafunction Table 4 4. DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices (Part 2 of 3) Bit External Bit Name Description 10 enadqsenablephasetransferreg octdelaysetting 16 dqshalfratebypass dqsbusoutdelaysetting Connects to the enaphasetransferreg port of the DQS Enable Control block to allow an additional negative edgetriggered register to be added to the DQS enable control path to satisfy the setup or hold time requirement for the phase transfer. Connects to the delayctrlin port of the D5 delay chain. Controls the dynamic OCT output register-to-i/o buffer delay chain (D5). For delay values, refer to the Programmable IOE Delay section in the Arria V Device Datasheet. For delay values, refer to the Programmable IOE Delay section in the Cyclone V Device Datasheet. Sets the multiplexers in the DQS enable logic, OCT logic, and FIFO control logic to dynamically switch from half-rate to full-rate configuration. Connects to the delayctrlin port of the read DQS D4 delay chain. Controls the delay tuning of the DQS signal feeding into the DQS bus. Legend in Figure 4 4 Default (Binary) I 0 J K 0 L Min. 0: Disable Neg-Edge Register 1: Enable Neg-Edge Register intrinsic delay 775 ps + intrinsic delay 25 ps 0: Engage Half-Rate Register 1: Bypass Half-Rate Register intrinsic delay Max. 775 ps + intrinsic delay Inc. 25 ps Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 17 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

44 ALTDQ_DQS2 Megafunction January 2013 Altera Corporation Table 4 4. DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices (Part 3 of 3) Bit External Bit Name Description 22 postamblephaseinvert postamblephasesetting Not mapped to any port Connects to the phaseinvertctrl port of the clock phase select block to select between the non-inverted and inverted output. This clock phase select block is used to level the postamble clock (in leveling multiplexer). This setting allows the phase output from the delay chain to be inverted to gain additional phases. Connects to the phasectrlin port of the clock phase select block to select between phase shifts of 0, 45, 90, and 135. This particular clock phase select block is used to level the postamble clock (in leveling multiplexer). Unconfigurable bits. Always set bits to its default value. Legend in Figure 4 4 Default (Binary) M 0 N 00 Min. 0 = Non-invert 1 = Invert 00 = 0 01 = = = 135 Max. Inc Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction

45 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction 4 19 Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Figure 4 4. I/O and DQS Delay Chains for Arria V and Cyclone V Devices DQS Logic Block From Core D5_OCT Dynamic OCT Control (2) J OE Register OE from Core 2 Half Data Rate Block PRN D Q OE Register PRN D Q B V CCIO Write Data from Core clkout 4 Half Data Rate Block Output Register PRN D Q Output Register PRN D Q D3_0 Delay F Programmable Current Strength and Slew Rate Control C D5 Delay D5 Delay Open Drain Output Buffer Input Buffer Programmable Pull-Up Resistor From OCT Calibration Block On-Chip Termination DQ To Core Bus Hold Circuit To Core D3_1 Delay D Mode D1 Delay A Input Register PRN D Q Clock Select E Read FIFO Clock Select Read Data to Core 4 Latency Shifter FIFO I rdclk Read FIFO Input Register PRN D Q Input Register PRN D Q Clock Signal from Core Leveling Delay Chain Clock Phase Select Data Valid FIFO DQS Enable Control DQS Delay Chain D4 Delay Chain N M K L DQS T11 Gating Delay Chain H G T11 Ungating Delay Chain January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

46 4 20 Chapter 4: Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Dynamic Reconfiguration for ALTDQ_DQS2 Megafunction Figure 4 5. An Example Usage of Dynamic Reconfiguration config_io_ena[7:0] config_dqs_io_ena[0:0] config_dqs_ena[0:0] config_data config_update Notes to Figure 4 5: (1) (2) (3) (4) (1) When the scanning process begins, assert each config_io_ena bit for 40 cycles to enable the 40 bits config_data (based on the I/O configuration block bits) for each DQ I/O. Each DQS group consists of a configuration block per one DQ pin. The config_ena_io is eight bit because the DQ pin width is set to 8. (2) Assert config_dqs_io_ena for 40 cycles to shift the 40 bits config_data (based on I/O configuration block bits) for the DQS pin. (3) Assert config_dqs_ena for 101 cycles to shift the 101 bits config_data (based on DQS configuration block bits) for the DQS logic. (4) Assert config_update for one cycle. The scan chain process is complete. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

47 5. Instantiating Megafunctions UG This section describes how to instantiate the ALTDQ_DQS2, ALTERA_PLL, ALTDLL, and ALT_OCT megafunctions. 1 You can apply the settings for Arria V devices for Cyclone V devices as well. Procedure This section describes the following steps: Instantiating the ALTDQ_DQS2 Megafunction Instantiating the ALTERA_PLL Megafunction on page 5 4 Instantiating the ALTDLL Megafunction on page 5 11 Instantiating the ALT_OCT Megafunction on page 5 15 Instantiating the ALTDQ_DQS2 Megafunction To instantiate the ALTDQ_DQS2 megafunction, perform the following steps: 1. In the Quartus II software, open either of the following files and restore the archived file into your working directory. For Arria V devices: 12.1_AV_BasicDesign.qar For Stratix V devices: 12.1_SV_BasicDesign.qar 2. On the Tools menu, click MegaWizard Plug-In Manager. 3. Select Create a new custom megafunction variation, and then click Next. 4. Under the Installed Plug-In category, expand the I/O folder and then select ALTDQ_DQS2 v12.1, and Verilog HDL, and type your desired file name in the What name do you want for the output file field. 5. Click Next Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered ALTDQ_DQS2 Megafunction January 2013 Subscribe

48 5 2 Chapter 5: Instantiating Megafunctions 6. On the Parameter Settings tab, on the General page, specify the parameters as shown in Figure 5 1 for Stratix V devices and Figure 5 2 for Arria V devices. These parameters configure the general settings for the ALTDQD_DQS2 instance. Figure 5 1. ALTDQ_DQS2 Parameter Settings for Stratix V Devices ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

49 Chapter 5: Instantiating Megafunctions 5 3 Figure 5 2. ALTDQ_DQS2 Parameter Settings for Arria V Devices 7. Click Finish. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

50 5 4 Chapter 5: Instantiating Megafunctions Instantiating the ALTERA_PLL Megafunction To instantiate the ALTERA_PLL megafunction, perform the following steps: 1. On the Tools menu, click MegaWizard Plug-In Manager. 2. Select Create a new custom megafunction variation, and then click Next. 3. Under the Installed Plug-In category, expand the I/O folder and then select ALTERA_PLL v12.1, and Verilog HDL, and type your desired file name in the What name do you want for the output file field. 4. Click Next. 5. On the General tab, specify the parameters as shown in Figure 5 3 and Figure 5 4. Figure 5 3. ALTERA_PLL Megafunction General Tab Settings for Arria V and Stratix V Devices ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

51 Chapter 5: Instantiating Megafunctions 5 5 Figure 5 4. ALTERA_PLL Megafunction General Tab Settings for Arria V and Stratix V Devices January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

52 5 6 Chapter 5: Instantiating Megafunctions 6. On the Clock Switchover tab, specify the parameters as shown in Figure 5 5. Figure 5 5. ALTERA_PLL Megafunction Clock Switchover Tab Settings for Arria V and Stratix V Devices ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

53 Chapter 5: Instantiating Megafunctions On the Cascading tab, specify the parameters as shown in Figure 5 6. Figure 5 6. ALTERA_PLL Megafunction Cascading Tab Settings for Arria V and Stratix V Devices January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

54 5 8 Chapter 5: Instantiating Megafunctions 8. On the MIF Streaming tab, specify the parameters as shown in Figure 5 7. Figure 5 7. ALTERA_PLL Megafunction MIF Streaming Tab Settings for Arria V and Stratix V Devices ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

55 Chapter 5: Instantiating Megafunctions On the Settings tab, specify the parameters as shown in Figure 5 8. Figure 5 8. ALTERA_PLL Megafunction Settings Tab for Arria V and Stratix V Devices January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

56 5 10 Chapter 5: Instantiating Megafunctions 10. On the Settings tab, specify the parameters as shown in Figure 5 9. Figure 5 9. ALTERA_PLL Megafunction Advanced Parameters Tab Settings for Arria V and Stratix V Devices 11. Click Finish. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

57 Chapter 5: Instantiating Megafunctions 5 11 Instantiating the ALTDLL Megafunction To instantiate the ALTDLL megafunction, perform the following steps: 1. On the Tools menu, click MegaWizard Plug-In Manager. 2. Select Create a new custom megafunction variation, and then click Next. 3. Under the Installed Plug-In category, expand the I/O folder and then select ALTDLL and Verilog HDL, and type your desired file name in the What name do you want for the output file field. 4. Click Next. 5. On the Parameter Settings tab, on the General page, specify the parameters as shown in Figure Figure ALTDLL Megafunction Parameter Settings Tab for Arria V and Stratix V Devices 6. Click Next. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

58 5 12 Chapter 5: Instantiating Megafunctions 7. In the DLL Offset Controls/Optional Ports section, on the General page, specify the parameters as shown in Figure Figure ALTDLL Megafunction DLL Offset Controls/Optional Ports Section Settings for Arria V and Stratix V Devices 8. Click Next. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

59 Chapter 5: Instantiating Megafunctions On the Simulation Model tab, specify the parameters as shown in Figure Figure ALTDLL Megafunction Simulation Model Tab Settings for Arria V and Stratix V Devices 10. Click Next. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

60 5 14 Chapter 5: Instantiating Megafunctions 11. In the Summary tab, specify the parameters as shown in Figure Figure ALTDLL Megafunction Summary Tab Settings for Arria V and Stratix V Devices 12. Click Finish. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

61 Chapter 5: Instantiating Megafunctions 5 15 Instantiating the ALT_OCT Megafunction To instantiate the ALT_OCT megafunction, perform the following steps: 1. On the Tools menu, click MegaWizard Plug-In Manager. 2. Select Create a new custom megafunction variation, and then click Next. 3. Under the Installed Plug-In category, expand the I/O folder and then select ALTOCT and Verilog HDL, and type your desired file name in the What name do you want for the output file field. 4. Click Next. 5. On the Parameter Settings tab, on the General page, specify the parameters as shown in Figure Figure ALT_OCT Megafunction Parameter Settings Tab for Arria V and Stratix V Devices January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

62 5 16 Chapter 5: Instantiating Megafunctions 6. Click Next. 7. In the EDA tab, specify the parameters as shown in Figure Figure ALT_OCT Megafunction EDA Tab Settings for Arria V and Stratix V Devices 8. Click Next. ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

63 Chapter 5: Instantiating Megafunctions On the Summary tab, specify the parameters as shown in Figure Figure ALT_OCT Megafunction Summary Tab Settings for Arria V and Stratix V Devices 10. Click Finish. January 2013 Altera Corporation ALTDQ_DQS2 Megafunction

64 5 18 Chapter 5: Instantiating Megafunctions Figure 5 17 shows the block diagram for the ALTDQ_DQS2, ALTERA_PLL, ALTDLL, and ALT_OCT megafunctions for the Stratix V devices. Figure ALTDQ_DQS2, ALTERA_PLL, ALTDLL, and ALT_OCT Megafunctions Block Diagram for Stratix V Devices for Stratix V Devices ALTDQ_DQS2 Megafunction January 2013 Altera Corporation

65 Chapter 5: Instantiating Megafunctions 5 19 Figure ALTDQ_DQS2, ALTERA_PLL, ALTDLL, and ALT_OCT Megafunctions Block Diagram for Stratix V Devices for Arria V Devices January 2013 Altera Corporation ALTDQ_DQS2 Megafunction