Chapter 5 Hardware Software co-simulation Hardware Software co-simulation of a multiple image encryption technique has been described in the present study. Proposed multiple image encryption technique is based on Latin Square Image Cipher (LSIC). First, a carrier image based on Latin Square is generated by using 256 bits length key. XOR operation is applied between an input image and Latin Square Image to generate an encrypted image. Then XOR operation is applied between encrypted image and second input image to encrypt second image. This process is continued till n th input image. Hardware co-simulation of the proposed multiple image encryption technique is achieved by using Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. Proposed technique is validated using hardware software co-simulation method. 107
5.1 Matlab and Simulink MATLAB is a high level technical computing language and algorithm development tool that can be used in several applications such as data visualization/analysis, numerical analysis, signal processing, control design, etc. Using the MATLAB software, solution can be achieved faster than traditional programming languages, such as C, C++. Add on toolboxes are a collections of special purpose MATLAB functions that are available separately. These software patches extend the MATLAB capabilities to solve particular classes of problems in these application areas. MATLAB provides a number of features, of which the most important ones are: Development environment for managing code, files, and data Interactive tools for iterative exploration, design, and problem solving Mathematical functions for linear algebra, statistics, Fourier analysis, filtering, optimization, and numerical integration 2-D and 3-D graphics functions for visualizing data Tools for building custom graphical user interfaces Functions for integrating MATLAB based algorithms with external applications and languages, such as C, C++, The MATLAB language is a high-level language with control flow statements, functions, data structures, input/output, and object-oriented programming features. The available libraries are vast collection of computational algorithms from basic functions such as arithmetic and trigonometric functions to complex functions such as matrix operations and Fourier transforms. Simulink is a software package for modeling, simulating, and analyzing dynamical systems. It supports linear and nonlinear systems, modeled in continuous time, sampled time, or a hybrid of the two. Systems can also be 108
multirate, i.e., have different parts that are sampled or updated at different rates.simulinkis a graphical representation of systems, differential equations, or problems encountered in engineering fields. Blocks can be assembled to reproduce almost anything as long as it can be modeled mathematically. Simulink has become an important part of aeronautical, astronautical, computer, electrical, and mechanical engineering programs and industries. Its necessary to evaluate performance of image processing algorithms on reconfigurable hardware. Simulink can be used to control systems with the correct hardware and software. 5.2 Xilinks system generator Simulink is a software tool from MATLAB for modeling, simulating, and analyzing dynamic systems. The Xilinx System Generator runs as part of Simulink. The System Generator elements bundled as the Xilinx Blockset, appear in the Simulink library browser. System Generator works within the Simulink model based design methodology. Often an executable specification is created using the standard Simulink block sets. This specification can be designed using floating point numerical precision and without hardware detail. Once the functionality and basic dataflow issues have been defined, System Generator can be used to specify the hardware implementation details for specific Xilinx device. System Generator uses the Xilinx DSP blockset for Simulink and will automatically invoke Xilinx Core Generator to generate highly optimized netlists for the DSP building blocks. System Generator can execute all the downstream implementation tools to product a bitstream for programming the FPGA. An optional testbench can be created using test vectors extracted from the Simulink environment for use with the simulator. Xilinx System Generator (XSG) is an integrated design environment (IDE) for FPGAs, which uses Simulink, as a development environment and is presented in the form of blockset. The architecture for filters, pixel by 109
pixel and regions filters for image processing using Xilinx System Generator has been proposed by Alba M. Snchez G. et al [60]. This architecture offer an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explore important aspects concerned to hardware implementation. Ana Toledo Moreo et al [61] shown that, how the Xilinx system generator (XSG) environment can be used to develop hardware-based computer vision algorithms from a system level approach, which makes it suitable for developing co-design environments. An efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator has been presented by Mrs. S. Allin Christe et al [62]. This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspects concerned to hardware implementation. V.Elamaran et al [63] have explained the FPGA implementation of Spatial Image Filters using Xilinx System Generator. 5.2.1 Dual Image Encryption Hardware Software co-simulation of a multiple image encryption technique has been described in the present study. Proposed multiple image encryption technique is based on Latin Square Image Cipher (LSIC). First, a carrier image based on Latin Square is generated by using 256 bits length key. XOR operation is applied between an input image and Latin Square Image to generate an encrypted image. Then XOR operation is applied between encrypted image and second input image to encrypt second image. This process is continued till n th input image. The proposed multiple image encryption technique is implemented Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. Proposed technique is validated using hardware software co-simulation method. Figure 5.1 shows the simulation diagram of dual image encryption. Figure 5.2 shows the input and output images of dual image encryption using hardware-software co-simulation. 110
Figure 5.1: Simulation of Dual Image Encryption using Hardware-Software co-simulation. Figure 5.2: Input and output images of Dual Image Encryption using Hardware-Software co-simulation. 111
5.2.2 Multiple Image Encryption Here multiple image encryption technique is based on Latin Square Image Cipher (LSIC). First, a carrier image based on Latin Square is generated by using 256 bits length key. XOR operation is applied between an input image and Latin Square Image to generate an encrypted image. Then XOR operation is applied between encrypted image and second input image to encrypt second image. This process is continued till n th input image. Hardware cosimulation of this multiple image encryption technique is achieved by using Xilinx System Generator (XSG). This encryption technique is modeled using Simulink and XSG Block set and synthesized onto Virtex 2 pro FPGA device. Figure 5.3 shows the simulation diagram of dual image encryption. Figure 5.4 and figure 5.5 shows the input and output images of dual image encryption using hardware-software co-simulation. Figure 5.6 and figure 5.7 shows the histograms of input and output images respectively. Multiple Image Encryption using Hardware-Software co- Figure 5.3: simulation. 112
Figure 5.4: Input images for Multiple Image Encryption. Figure 5.5: Encrypted images from Multiple Image Encryption. 113
Figure 5.6: Histograms of Input images Figure 5.7: Histograms of output images 5.3 Implementation of Image Encryption on FPGA FPGA implementation is carried out using Xilinx ISE 8.1 and Vertex 2 pro FPGA device. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used as programming language for implementation. FPGA implementation done for image encryption, image shuffling and partial image encryption using SCAN methodology - Latin Square 114
Image cipher. RTL (Register Transfer Level) diagram of these methods are shown in figure 5.8, 5.9 and 5.10. Resource utilization summary of these methods are tabulated in table 5.1, 5.2 and 5.3. 5.3.1 Image encryption using Latin Square Image cipher (b) (a) (c) Figure 5.8: FPGA implementation of Image encryption using Latin Square Image cipher (a) Gate level design-1 (b)gate level design-2 (c) Gate level design-3. 115
5.3.2 Image Shuffling using Latin Square Image cipher (a) Figure 5.9: FPGA implementation of Image shuffling using Latin Square Image cipher 116
5.3.3 Image encryption using SCAN methodology and mapping operation 117 (a) Figure 5.10: FPGA implementation of Image encryption using SCAN methodology and mapping operation
Table 5.1: Device Utilization Summary for Image encryption using Latin Square Image cipher Logic Utilization Used Available Utilization Number of Slices 1178 3584 32% Number of 4 input LUTs 2048 7168 28 % Number of bonded IOBs 6144 141 4357% Table 5.2: Device Utilization Summary for Image shuffling using Latin Square Image cipher Logic Utilization Used Available Utilization Number of Slices 512 3584 14% Number of 4 input LUTs 1024 7168 14% Number of bonded IOBs 320 141 226% Table 5.3: Device Utilization Summary for Image encryption using SCAN methodology and mapping operation Logic Utilization Used Available Utilization Number of Slices 530 3584 14% Number of 4 input LUTs 1056 7168 14% Number of bonded IOBs 352 141 249 % (a) (b) (c) Figure 5.11: Resource utilization interms of Number of slices, Number of 4 input LUTs and Number of bonded IOBs for (a) Image encryption using Latin Square Image cipher (b)image shuffling using Latin Square Image cipher (c)image encryption using SCAN methodology and mapping operation 118