HIGH SPEED 3K x 8 3.3 STATIC CMOS RAM FEATURES 3.3 Power Supply High Speed (Equal Access and Cycle Times) 1///5 (Commercial) //5 (Industrial) Low Power Single 3.3 olts ±.3olts Power Supply Easy Memory Expaion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages 8-Pin TSOP and SOJ DESCRIPTION The P3C6 is a 6,144-bit high-speed CMOS static RAM organized as 3Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3±.3 tolerance power supply. Access times as fast as 1 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power coumption to a low level. The P3C6 is a member of a family of PACE RAM products offering fast access times. The P3C6 device provides asynchronous operation with matching access and cycle times. Memory locatio are specified on address pi A to A 14. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remai HIGH. By presenting the address under these conditio, the data in the addressed memory location is presented on the data input/output pi. The input/output pi stay in the HIGH Z state when either CE or OE is HIGH or WE is LOW. Package optio for the P3C6 include 8-pin TSOP and SOJ packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS SOJ (J5) 19B TOP IEW See end of datasheet for TSOP pin configuration 1 Revised August 6
RECOMMENDED OPERATING TEMPERATURE & SUPPLY OLTAGE Temperature Range (Ambient) Supply oltage Commercial ( C to 7 C) 3. 3.6 Industrial (-4 C to 85 C) 3. 3.6 MAIMUM RATINGS (1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditio in excess of those given in the operational sectio of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol Parameter Unit Supply oltage with Respect to GND -.5 7. TERM Terminal oltage with Respect to GND (up to 7.) -.5 +.5 T A Operating Ambient Temperature -4 85 C S TG Storage Temperature -55 C I OUT Output Current into Low Outputs 5 ma I LAT Latch-up Current > ma DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply oltage) () Symbol Parameter Test Conditio Unit OH Output High oltage (I/O - I/O 7 ) I OH = 4mA, = 3..4 OL Output Low oltage (I/O - I/O 8 ) I OL = 8 ma I OL = 1 ma.4.5 IH Input High oltage. +.3 IL Input Low oltage -.5 (3).8 I LI Input Leakage Current GND IN -5 +5 µa I LO Output Leakage Current GND OUT CE = -5 +5 µa I SB Current TTL Standby Current = 3.6, I OUT = ma CE = ma I SB1 Current CMOS Standby Current = 3.6, I OUT = ma CE = 3 ma Page of 1
CAPACITANCES (4) ( = 5., T A = 5 C, f = 1. MHz) Symbol Parameter Test Conditio Max Unit C IN Input Capacitance IN = 1 pf C OUT Output Capacitance OUT = 1 pf POWER DISSIPATION CHARACTERISTICS S. SPEED Temperature Test Symbol Parameter Unit Range -1 - - -5 Conditio Commercial * 11 1 ma I 95 9 CC Dynamic Operating Current Industrial * N/A 1 11 ma *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE, and WE IL (max), OE is high. Switching inputs are and 3. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply oltage) Symbol Parameter -1 - - -5 Unit t RC Read Cycle Time 1 5 t AA Address Access Time 1 5 t AC t OH Chip Enable Access Time Output Hold from Address Change 1 5 t LZ Chip Enable to Output in Low Z t HZ Chip Disable to Output in High Z 7 8 9 1 t OE Output Enable Low to Data alid 7 9 11 1 t OLZ Output Enable Low to Low Z t OHZ Output Enable High to High Z 6 7 9 1 t PU Chip Enable to Power Up Time t PD Chip Disable to Power Down Time 1 Page 3 of 1
TIMING WAEFORM OF READ CYCLE NO. 1 (OE OE CONTROLLED) (5) TIMING WAEFORM OF READ CYCLE NO. (ADDRESS CONTROLLED) (5,6) TIMING WAEFORM OF READ CYCLE NO. 3 (CE CONTROLLED) (5,7) Notes: 1. Stresses greater than those listed under MAIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to MAIMUM rating conditio for extended periods may affect reliability.. Extended temperature operation guaranteed with 4 linear feet per minute of air flow. 3. Traient inputs with IL and I IL not more negative than 3. and 1mA, respectively, are permissible for pulse widths up to. 4. This parameter is sampled and not 1% tested. 5. WE is HIGH for READ cycle. 6. CE is LOW and OE is LOW for READ cycle. 7. ADDRESS must be valid prior to, or coincident with CE traition LOW. 8. Traition is measured ± m from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 1% tested. 9. Read Cycle Time is measured from the last valid address to the first traitioning address. Page 4 of 1
AC CHARACTERISTICS WRITE CYCLE (Over Recommended Operating Temperature & Supply oltage) Symbol t WC t CW t AW t AS Parameter Write Cycle Time Chip Enable Time to End of Write Address alid to End of Write Address Set-up Time -1 1 1 1 - - 1 18 1 18-5 5 t WP Write Pulse Width 9 11 18 Unit t AH Address Hold Time t DW Data alid to End of Write 8 1 1 t DH Data Hold Time t WZ Write Enable to 7 8 1 11 Output in High Z t OW Output Active from 3 3 3 3 End of Write TIMING WAEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1,11) Notes: 1. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show t WZ and t OW. 1. If CE goes HIGH simultaneously with WE HIGH, the output remai in a high impedance state 13. Write Cycle Time is measured from the last valid address to the first traitioning address. Page 5 of 1
TIMING WAEFORM OF WRITE CYCLE NO. (CE CE CONTROLLED) (1) AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3. Mode CE OE WE I/O Power Input Rise and Fall Times 3 Standby H High Z Standby Input Timing Reference Level 1.5 Output Timing Reference Level 1.5 Output Load See Figures 1 and Standby D OUT Disabled Read L L H L H H High Z High Z D OUT Standby Active Active Write L L High Z Active Figure 1. Output Load Figure. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P3C6, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the and ground planes directly up to the contactor fingers. A.1 µf high frequency capacitor is also required between and ground. To avoid signal reflectio, proper termination must be used; for example, a 5Ω test environment should be terminated into a 5Ω load with 1.73 (Thevenin oltage) at the comparator input, and a 116Ω resistor must be used in series with D OUT to match 166Ω (Thevenin Resistance). Page 6 of 1
DATA RETENTION CHARACTERISTICS Symbol DR Parameter for Data Retention Test Condito Min. Typ.* =. 3. Max =. 3. Unit I CCDR Data Retention Current CE., 1 6 9 µa t CDR t R Chip Deselect to Data Retention Time Operation Recovery Time IN. or IN. t RC *T A = +5 C t RC = Read Cycle Time This parameter is guaranteed but not tested. DATA RETENTION WAEFORM TSOP PIN CONFIGURATION Page 7 of 1
ORDERING INFORMATION SELECTION GUIDE The P3C6 is available in the following temperature, speed and package optio. Temperature Speed Package Range 1 5 Commercial TSOP -1TC -TC -TC -5TC Plastic SOJ -1JC -JC -JC -5JC Industrial TSOP N/A -TI -TI -5TI Plastic SOJ N/A -JI -JI -5JI N/A = Not Available Page 8 of 1
Pkg # # Pi J5 8 (3 mil) Symbol A.1.148 A1.78 - b.14. C.7.11 D.7.73 e E.5 BSC.335 BSC E1.9.3 E.67 BSC Q.5 - SOJ SMALL OUTLINE IC PACKAGE Pkg # # Pi T1 8 Symbol A.39.47 A.36.4 b.7.11 D.461.469 E.311.319 e. BSC H D.5.535 TSOP THIN SMALL OUTLINE PACKAGE Page 9 of 1
REISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM1 P3C6 HIGH SPEED 3K x 8 3.3 STATIC CMOS RAM RE. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE OR 1997 DAB New Data Sheet A Oct-5 JDB Change logo to Pyramid B Aug-6 JDB Updated SOJ package information Page 1 of 1