CMOS Static RAM 1 Meg (K x -Bit) Revolutionary Pinout IDT714 Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access and cycle times Commercial: //2 Industrial: /2 One Chip Select plus one Output Enable pin Bidirectional inputs and outputs directly TTL-compatible Low power coumption via chip deselect Available in a 32-pin 4 mil Plastic SOJ Description The IDT714 is a 1,4,576-bit high-speed static RAM organized as K x It is fabricated using high-performance, high-reliability CMOS technology This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs The JEDEC centerpower/gnd pinout reduces noise generation and improves system performance The IDT714 has an output enable pin which operates as fast as 6, with address access times as fast as available All bidirectional inputs and outputs of the IDT714 are TTL-compatible and operation is from a single 5V supply Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation The IDT714 is packaged in a 32-pin 4 mil Plastic SOJ Functional Block Diagram A DECODER 1,4,576-BIT MEMORY ARRAY A16 I/O -I/O7 I/O CONTROL, WE OE CONTROL LOGIC 3514 drw 1 213 Integrated Device Technology, Inc 1 APRIL 213 DSC-3514/11
IDT714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Pin Configuration A A1 A2 A3 I/O I/O1 VCC GND I/O2 I/O3 WE A4 A5 A6 1 2 3 4 5 6 SO32-3 7 9 1 11 32 31 3 29 2 27 26 25 24 23 22 21 13 2 14 19 1 16 A7 17 SOJ Top View A16 A A14 A13 OE I/O7 I/O6 GND VCC I/O5 I/O4 A A11 A1 A9 A 3514 drw 2, Absolute Maximum Ratings (1) Symbol Rating Value Unit VTERM (2) Terminal Voltage with Respect to GND 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied Exposure to absolute maximum rating conditio for extended periods may affect reliabilty 2 VTERM must not exceed Vcc + 5V Capacitance (TA = +25 C, f = 1MHz) -5 to +7 (2) V TA Operating Temperature to +7 o C TBIAS TSTG Temperature Under Bias Storage Temperature -55 to +5 o C -55 to +5 o C PT Power Dissipation 125 W IOUT DC Output Current 5 ma 3514 tbl 2 Truth Table (1,2) OE WE I/O Function L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected - Standby (ISB) VHC (3) X X High-Z Deselected - Standby (ISB1) 1 H = VIH, L = VIL, x = Don't care 2 VLC = 2V, VHC = VCC -2V 3 Other inputs VHC or VLC 3514 tbl 1 Symbol Parameter (1) Conditio Max Unit CIN Input Capacitance VIN = 3dV pf CI/O I/O Capacitance VOUT = 3dV pf 3514 tbl 3 NOTE: 1 This parameter is guaranteed by device characterization, but is not production tested Recommended Operating Temperature and Supply Voltage Grade Temperature GND VCC Commercial C to +7 C V 5V ± 1% Industrial 4 C to +5 C V 5V ± 1% 3514 tbl 4 Recommended DC Operating Conditio Symbol Parameter Min Typ Max Unit VCC Supply Voltage 45 5 55 V GND Ground V VIH Input High Voltage 22 VCC +5 V VIL Input Low Voltage -5 (1) V 3514 tbl 5 642 2
IDT 714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VCC = 5V ± 1%, Commercial and Industrial Temperature Ranges) Symbol Parameter Test Conditio Min Max Unit ILI Input Leakage Current VCC = Max, VIN = GND to VCC 5 µa ILO Output Leakage Current VCC = Max, = VIH, VOUT = GND to VCC 5 µa VOL Output Low Voltage IOL = ma, VCC = Min 4 V VOH Output High Voltage IOH = 4mA, VCC = Min 24 V 3514 tbl 6 DC Electrical Characteristics (1) (VCC = 5V ± 1%, VLC = 2V, VHC = VCC 2V) 714S 714S 714S2 Symbol Parameter Com'l Com'l Ind Com'l Ind Unit ICC ISB Dynamic Operating Current 16 5 5 14 14 ma < VIL, Outputs Open, VCC = Max, f = fmax (2) Standby Power Supply Current (TTL Level) 4 4 4 4 4 ma > VIH, Outputs Open, VCC = Max, f = fmax (2) ISB1 Full Standby Power Supply Current (CMOS Level) > VHC, Outputs Open, VCC = Max, f = (2) VIN < VLC or VIN > VHC 1 1 1 1 1 ma 1 All values are maximum guaranteed values 2 fmax = 1/tRC (all address inputs are cycling at fmax); f = mea no address input lines are changing 3514 tbl 7 AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3V 3 15V 15V See Figure 1 and 2 3514 tbl AC Test Loads 5V 5V 4Ω 4Ω DATA OUT DATA OUT 3pF 255Ω 3514 drw 3 5pF* 255Ω 3514 drw 4 Figure 1 AC Test Load *Including jig and scope capacitance Figure 2 AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) 642 3
IDT714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5V ± 1%, Commercial and Industrial Temperature Ranges) 714S (2) 714S 714S2 Symbol Parameter Min Max Min Max Min Max Unit READ CYCLE trc Read Cycle Time 2 taa Address Access Time 2 ta Chip Select Access Time 2 tclz (1) Chip Select to Output in Low-Z 3 3 3 tchz (1) Chip Deselect to Output in High-Z 6 7 toe Output Enable to Output Valid 6 7 tolz (1) Output Enable to Output in Low-Z tohz (1) Output Disable to Output in High-Z 5 5 7 toh Output Hold from Address Change 4 4 4 tpu (1) Chip Select to Power-Up Time tpd (1) Chip Deselect to Power-Down Time 2 WRITE CYCLE twc Write Cycle Time 2 taw Address Valid to End of Write tcw Chip Select to End of Write tas Address Set-up Time twp Write Pulse Width twr Write Recovery Time tdw Data Valid to End-of-Write 6 9 tdh Data Hold Time tow (1) Output active from End-of-Write 3 3 4 twhz (1) Write Enable to Output in High-Z 5 5 NOTE: 1 This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested 2 There is no industrial temperature offering for the speed grade 3514 tbl 9 642 4
IDT 714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No 1 (1) taa trc OE toe tolz DATAOUT (3) ta tclz HIGH IMPEDANCE tchz tohz DATAOUT VALID VCC SUPPLY CURRENT ICC ISB tpu tpd 3514 drw 5 Timing Waveform of Read Cycle No 2 (1,2,4) trc taa DATAOUT toh PREVIOUS DATAOUT VALID toh DATAOUT VALID 3514 drw 6 1 WE is HIGH for Read Cycle 2 Device is continuously selected, is LOW 3 Address must be valid prior to or coincident with the later of traition LOW; otherwise taa is the limiting parameter 4 OE is LOW 5 Traition is measured ±2mV from steady state 642 5
IDT714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No 1 (WE Controlled Timing) (1,2,4) twc taw WE tas twhz (2) twp twr tow tchz DATAOUT (3) HIGH IMPEDANCE tdw tdh (3) DATAIN DATAIN VALID 3514 drw 7 Timing Waveform of Write Cycle No 2 ( Controlled Timing) (1,4) twc taw WE tas tcw twr tdw tdh DATAIN DATAIN VALID 3514 drw 1 A write occurs during the overlap of a LOW and a LOW WE 2 OE is continuously HIGH During a WE controlled write cycle with OE LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp 3 During this period, I/O pi are in the output state, and input signals must not be applied 4 If the LOW traition occurs simultaneously with or after the WE LOW traition, the outputs remain in a high impedance state must be active during the tcw write period 5 Traition is measured ±2mV from steady state 642 6
IDT 714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Ordering Information 714 Device Type S Power XX Speed X Package X X Process/ Temperature Range X Blank Tube or Tray Tape and Reel Blank I Commercial (C to +7C) Industrial ( 4C to +5C) G Green Y 4-mil SOJ (SO32-3) * 2 Speed in nanoseconds 3514 drw 9 * No industrial temp on speed 642 7
IDT714 CMOS Static RAM 1 Meg (K x -bit) Revolutionary Pinout Commercial and Industrial Temperature Ranges Datasheet Document History /5/99: Updated to new format Pg 3 Removed military entries on DC table Pg 4 Removed Note 1 and renumbered footnotes Pg 6 Revised footnotes on Write Cycle No 1 diagram /13/99: Pg Added Datasheet Document History 9/3/99: Pg 1, 3, 4, 7 Added,, and 2 industrial temperature speed grade offerings 2/1/: Pg 3 Revise ISB for Industrial Temperature offerings to meet commerical specificatio 3/14/: Pg 3 Revised ISB to accomidate speed functionality 4/1/: Pg4 Tightened taw, tcw, twp and tdw within the AC Electrical Characteristics /9/: Not recommended for new desig 2/1/1: Removed "Not recommended for new desig" 1/23/: Pg7 Removed "IDT" from the orderable part number 4/2/13: Pg1 Removed speed from the Industrial temp offering Removed IDT in reference to fabrication Pg3 Removed the industrial speed grade information from the DC Electrical Chars table 7 Pg4 Added footnote 2 to AC Electrical Chars table 9 to indicate that there is no industrial speed Pg7 Added Tape & Reel and Green designators to the ordering information Added a footnote to the ordering information to indicate that there is no industrial speed offering CORPORATE HEADQUARTERS for SALES: 624 Silver Creek Valley Road -345-7 or San Jose, CA 9513 4-24-2 fax: 4-24-2775 wwwidtcom for Tech Support: sramhelp@idtcom 4-24-4532 The IDT logo is a registered trademark of Integrated Device Technology, Inc 642