Objectives Chapter 5: Computer Systems Organization Invitation to Computer Science, C++ Version, Third Edition In this chapter, you will learn about: The components of a computer system Putting all the pieces together the Von Neumann architecture The future: non-von Neumann architectures Invitation to Computer Science, C++ Version, Third Edition 2 Introduction Figure 5.1 The Concept of Abstraction Computer organization examines the computer as a collection of interacting functional units Functional units may be built out of the circuits already studied Higher level of abstraction assists in understanding by reducing complexity Invitation to Computer Science, C++ Version, Third Edition 3 Invitation to Computer Science, C++ Version, Third Edition 4 The Components of a Computer System Von Neumann architecture has four functional units: Memory Input/Output Arithmetic/Logic unit Control unit Sequential execution of instructions Stored program concept Figure 5.2 Components of the Von Neumann Architecture Invitation to Computer Science, C++ Version, Third Edition 5 Invitation to Computer Science, C++ Version, Third Edition 6 1
Memory and Cache Memory and Cache Information stored and fetched from memory subsystem Random Access Memory maps addresses to memory locations Cache memory keeps values currently in use in faster memory to speed access times RAM (Random Access Memory) Memory made of addressable cells Current standard cell size is 8 bits All memory cells accessed in equal time Memory address Unsigned binary number N long Address space is then 2 N cells Invitation to Computer Science, C++ Version, Third Edition 7 Invitation to Computer Science, C++ Version, Third Edition 8 Memory and Cache Figure 5.3 Structure of Random Access Memory Parts of the memory subsystem Fetch/store controller Fetch: retrieve a value from memory Store: store a value into memory Memory address register (MAR) Memory data register (MDR) Memory cells, with decoder(s) to select individual cells Invitation to Computer Science, C++ Version, Third Edition 9 Invitation to Computer Science, C++ Version, Third Edition 10 Memory and Cache Memory and Cache Fetch operation The address of the desired memory cell is moved into the MAR Fetch/store controller signals a fetch, accessing the memory cell The value at the MAR s location flows into the MDR Store operation The address of the cell where the value should go is placed in the MAR The new value is placed in the MDR Fetch/store controller signals a store, copying the MDR s value into the desired cell Invitation to Computer Science, C++ Version, Third Edition 11 Invitation to Computer Science, C++ Version, Third Edition 12 2
Memory and Cache Memory register Very fast memory location Given a name, not an address Serves some special purpose Modern computers have dozens or hundreds of registers Figure 5.7 Overall RAM Organization Invitation to Computer Science, C++ Version, Third Edition 13 Invitation to Computer Science, C++ Version, Third Edition 14 Cache Memory Memory access is much slower than processing time Faster memory is too expensive to use for all memory cells Locality principle Once a value is used, it is likely to be used again Small size, fast memory just for values currently in use speeds computing time Communication with outside world and external data storage Human interfaces: monitor, keyboard, mouse Archival storage: not dependent on constant power External devices vary tremendously from each other Invitation to Computer Science, C++ Version, Third Edition 15 Invitation to Computer Science, C++ Version, Third Edition 16 Volatile storage Information disappears when the power is turned off Example: RAM Nonvolatile storage Information does not disappear when the power is turned off Example: mass storage devices such as disks and tapes Mass storage devices Direct access storage device Hard drive, CD-ROM, DVD, etc. Uses its own addressing scheme to access data Sequential access storage device Tape drive, etc. Stores data sequentially Used for backup storage these days Invitation to Computer Science, C++ Version, Third Edition 17 Invitation to Computer Science, C++ Version, Third Edition 18 3
Direct access storage devices Data stored on a spinning disk Disk divided into concentric rings (sectors) Read/write head moves from one ring to another while disk spins Access time depends on: Time to move head to correct sector Time for sector to spin to data location Figure 5.8 Overall Organization of a Typical Disk Invitation to Computer Science, C++ Version, Third Edition 19 Invitation to Computer Science, C++ Version, Third Edition 20 I/O controller Intermediary between central processor and I/O devices Processor sends request and data, then goes on with its work I/O controller interrupts processor when request is complete Figure 5.9 Organization of an I/O Controller Invitation to Computer Science, C++ Version, Third Edition 21 Invitation to Computer Science, C++ Version, Third Edition 22 The Arithmetic/Logic Unit Actual computations are performed Primitive operation circuits Arithmetic (ADD, etc.) Comparison (CE, etc.) Logic (AND, etc.) Data inputs and results stored in registers Multiplexor selects desired output The Arithmetic/Logic Unit ALU process Values for operations copied into ALU s input register locations All circuits compute results for those inputs Multiplexor selects the one desired result from all values Result value copied to desired result register Invitation to Computer Science, C++ Version, Third Edition 23 Invitation to Computer Science, C++ Version, Third Edition 24 4
The Control Unit Manages stored program execution Task Fetch from memory the next instruction to be executed Decode it: determine what is to be done Figure 5.12 Using a Multiplexor Circuit to Select the Proper ALU Result Execute it: issue appropriate command to ALU, memory, and I/O controllers Invitation to Computer Science, C++ Version, Third Edition 25 Invitation to Computer Science, C++ Version, Third Edition 26 Machine Language Instructions Can be decoded and executed by control unit Parts of instructions Operation code (op code) Unique unsigned-integer code assigned to each machine language operation Address field(s) Memory addresses of the values on which operation will work Figure 5.14 Typical Machine Language Instruction Format Invitation to Computer Science, C++ Version, Third Edition 27 Invitation to Computer Science, C++ Version, Third Edition 28 Machine Language Instructions Operations of machine language Data transfer Move values to and from memory and registers Arithmetic/logic Perform ALU operations that produce numeric values Machine Language Instructions Operations of machine language Compares Set bits of compare register to hold result Branches Jump to a new memory address to continue processing Invitation to Computer Science, C++ Version, Third Edition 29 Invitation to Computer Science, C++ Version, Third Edition 30 5
Control Unit Registers And Circuits Parts of control unit Links to other subsystems Instruction decoder circuit Two special registers: Program Counter (PC) Stores the memory address of the next instruction to be executed Instruction Register (IR) Stores the code for the current instruction Figure 5.16 Organization of the Control Unit Registers and Circuits Invitation to Computer Science, C++ Version, Third Edition 31 Invitation to Computer Science, C++ Version, Third Edition 32 Putting All the Pieces Together the Von Neumann Architecture Subsystems connected by a bus Bus: wires that permit data transfer among them At this level, ignore the details of circuits that perform these tasks: Abstraction! Computer repeats fetch-decode-execute cycle indefinitely Figure 5.18 The Organization of a Von Neumann Computer Invitation to Computer Science, C++ Version, Third Edition 33 Invitation to Computer Science, C++ Version, Third Edition 34 The Future: Non-Von Neumann Architectures Physical limitations on speed of Von Neumann computers Non-Von Neumann architectures explored to bypass these limitations Parallel computing architectures can provide improvements: multiple operations occur at the same time The Future: Non-Von Neumann Architectures SIMD architecture Single instruction/multiple data Multiple processors running in parallel All processors execute same operation at one time Each processor operates on its own data Suitable for vector operations Invitation to Computer Science, C++ Version, Third Edition 35 Invitation to Computer Science, C++ Version, Third Edition 36 6
The Future: Non-Von Neumann Architectures MIMD architecture Multiple instruction/multiple data Multiple processors running in parallel Figure 5.21 A SIMD Parallel Processing System Each processor performs its own operations on its own data Processors communicate with each other Invitation to Computer Science, C++ Version, Third Edition 37 Invitation to Computer Science, C++ Version, Third Edition 38 Summary of Level 2 Focus on how to design and build computer systems Chapter 4 Binary codes Transistors Figure 5.22 Model of MIMD Parallel Processing Gates Circuits Invitation to Computer Science, C++ Version, Third Edition 39 Invitation to Computer Science, C++ Version, Third Edition 40 Summary of Level 2 Chapter 5 Von Neumann architecture Shortcomings of the sequential model of computing Parallel computers Summary Computer organization examines different subsystems of a computer: memory, input/output, arithmetic/logic unit, and control unit Machine language gives codes for each primitive instruction the computer can perform, and its arguments Von Neumann machine: sequential execution of stored program Parallel computers improve speed by doing multiple tasks at one time Invitation to Computer Science, C++ Version, Third Edition 41 Invitation to Computer Science, C++ Version, Third Edition 42 7