Continuing Moore s law

Continuing Moore s law MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017

Legal Disclaimer DISCLOSURES China Tech and Manufacturing Day 2017 occurs during Intel s Quiet Period, before Intel announces its 2017 third quarter financial and operating results. Therefore, presenters will not be addressing third quarter information during this year s program. Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as anticipates, expects, intends, goals, plans, believes, seeks, estimates, continues, may, will, would, should, could, and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management s expectations as of September 19-20, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company s expectations are set forth in Intel s earnings release dated July 27, 2017, which is included as an exhibit to Intel s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel s results is included in Intel s SEC filings, including the company s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC s website at www.sec.gov.

Intel innovation leadership Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership High-k Metal Gate Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm High-k Metal Gate Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership High-k Metal Gate Self Align Via Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm High-k Metal Gate Self Align Via Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership High-k Metal Gate Self Align Via FinFET Transistor Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm High-k Metal Gate Self Align Via FinFET Transistor Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership High-k Metal Gate Self Align Via FinFET Transistor Hyper Scaling Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm High-k Metal Gate Self Align Via FinFET Transistor Hyper Scaling ~3 years Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership Fin Contact High-k Metal Gate Self Align Via FinFET Transistor Hyper Scaling Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm Gate Hyper Scaling High-k Metal Gate Self Align Via FinFET Transistor Hyper Scaling ~3 years Hyper Scaling?? Intel leads the industry by at least 3 years in introducing major process innovations

Intel innovation leadership Fin Contact High-k Metal Gate Self Align Via FinFET Transistor Hyper Scaling Intel 90nm 65nm 45nm 32nm 22nm 14nm 10nm Year 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Gate Hyper Scaling Others 90nm 65nm 40nm 28nm 20nm 16nm 10nm High-k Metal Gate Self Align Via FinFET Transistor Hyper Scaling ~3 years Hyper Scaling?? Intel developed all the major logic process innovations used by our industry over the past 15 years

Logic area scaling 1 45nm.49x Logic Area Metric 32nm.45x Gate Pitch Logic Area (relative) 0.1 22nm Logic Cell Height Logic Cell Width 0.01 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Traditional logic area scaling was ~0.49x per generation using a gate pitch x cell height metric

Logic area scaling 1 45nm.49x Logic Area Metric 32nm.45x Gate Pitch Logic Area (relative) 0.1 22nm 14nm.37x.37x Logic Cell Height 10nm Logic Cell Width 0.01 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Hyper scaling on 14 nm and 10 nm provides better than normal logic area scaling

Logic area scaling 1 45nm.49x Logic Area Metric 32nm.45x Gate Pitch Logic Area (relative) 0.1 22nm 14nm.37x.37x Logic Cell Height 10nm Logic Cell Width but gate pitch x cell height is not a comprehensive transistor density metric 0.01 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date

Logic Transistor density metric 2-Input NAND Cell Complex Scan Flip-Flop Logic Cell Cell Height Cell Width Cell Width NAND2 Tr Count Scan Flip Flop Tr Count 0.6 x + 0.4 x = # Transistors / mm 2 NAND2 Cell Area Scan Flip Flop Cell Area Standard NAND+SFF metric is a more accurate estimate of logic transistor density

Logic Transistor density 100 10nm Intel 14nm 2.7x Transistor Density MTr / mm 2 10 32nm 22nm 2.1x 2.5x 60/40 NAND+SFF Density Metric 45nm 2.3x 1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Hyper scaling on 14 nm and 10 nm provides better than normal transistor density

Logic Transistor density 100 10nm Intel 14nm Transistor Density MTr / mm 2 10 32nm 22nm 60/40 NAND+SFF Density Metric 45nm 1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Transistor density improvements continue at a rate of ~doubling every 2 years

Logic Transistor density 100 Intel 14nm 10nm 100.8 MTr/mm 2 90.8 NAND 115.7 SFF 100.8 60/40 Transistor Density MTr / mm 2 10 32nm 22nm 15.3 37.5 MTr / mm 2 60/40 NAND+SFF Density Metric 45nm 7.5 3.3 1 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 HVM Wafer Start Date Transistor density improvements continue at a rate of ~doubling every 2 years

Microprocessor die area scaling 0.62x 100 mm 2 62 mm 2 0.62x Area 0.62x 0.62x 38.4 mm 2 23.8 mm 2 IO Logic SRAM IO Logic 100 SRAM mm 2 IO Logic 100 SRAM mm 2 IO Logic 100 SRAM mm 2 14.8 mm 2 IO Logic 100 SRAM mm 2 45 nm 32 nm 22 nm 14 nm 10 nm Normal microprocessor die area scaling has been ~0.62x per generation

Microprocessor die area scaling 100 mm 2 0.62x 62 mm 2 0.62x Area 38.4 mm 2 0.46x 0.43x IO Logic IO Logic IO Logic 17.7 mm 2 7.6 mm 2 IO Logic SRAM 100 SRAM mm 2 100 SRAM mm 2 100 SRAM mm 2 IO Logic 100 SRAM mm 2 45 nm 32 nm 22 nm 14 nm 10 nm Hyper scaling delivers 0.46-0.43x die area scaling on 14 nm and 10 nm

45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm Log Scale Log Scale Log Scale Cost per transistor mm 2 / Transistor (normalized) $ / mm 2 (normalized) $ / Transistor (normalized) x = Transistor area is scaling faster than normal

45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm Log Scale Log Scale Log Scale Cost per transistor mm 2 / Transistor (normalized) $ / mm 2 (normalized) $ / Transistor (normalized) x = Wafer cost is increasing

45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm Log Scale Log Scale Log Scale Cost per transistor mm 2 / Transistor (normalized) $ / mm 2 (normalized) $ / Transistor (normalized) x = Cost per transistor continues to come down

Transistor Performance (log scale) Dynamic Capacitance (log scale) Performance per Watt (log scale) Transistor performance and power Performance Power Performance per Watt 32nm 22nm 14nm Higher Performance 10nm Lower Power 10nm Better Perf/Watt 10nm 14nm 32nm 22nm 14nm 32nm 22nm 2009 2011 2013 2015 2017 2019 2021 Process Readiness Date 2009 2011 2013 2015 2017 2019 2021 Process Readiness Date 2009 2011 2013 2015 2017 2019 2021 Process Readiness Date Scaled transistors continue to provide improved performance per watt

Gate Innovation Enabled technology Pipeline 45 nm 32 nm 22 nm 14 nm 10 nm 7 nm 5 nm 3 nm Manufacturing Development Research III-V Contact III-V Transistors 3D Stacking Material Synthesis High-k Metal Gate FinFETs Contact over Gate 2D Materials Nanowires EUV Patterning 10nm SA Double Patterning SA Quad Patterning Interconnects Beyond CMOS Dense Memory Future options subject to change Wide range of options in research to continue Moore s Law

Summary Intel leads the industry in introducing innovations that enable scaling Hyper scaling on Intel 14 nm and 10 nm provides better-than-normal scaling while continuing to reduce cost per transistor and improve performance per watt Intel s research and development groups are exploring a wide range of novel technology options to continue scaling for the foreseeable future Moore s Law is alive and well at Intel