Verilog for Combinational Circuits

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Verilog for Combinational Circuits Lan-Da Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/

HDL Models of Combinational Circuits Modeling Styles Gate-level modeling using instantiations of predefined and user-defined primitive gates. Dataflow modeling using continuous assignments with keyword assign. Behavioral modeling using procedural assignments with keyword always. (Instantiations ~ the HDL counterpart of placing and connecting parts on a circuit board) 2

Gate-level Modeling The four-valued logic truth tables for the and, or, xor, and not primitives Unknown High impedance 3

Gate-level Modeling Example (identifiers having multiple bit widths, call vectors): output [0: 3] D; wire [7: 0] SUM; 1. The first statement declares an output vector D with four bits, 0 through 3. 2. The second declares a wire vector SUM with eight bits numbered 7 through 0. 4

Gate-level Modeling 1st once 5

1-Bit Half Adder Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 = (10) 2 two input variables: x, y two output variables: C (carry), S (sum) truth table S = x'y+xy'=x y= (x+y)(x'+y') C = xy= (x'+y')' S' = xy+x'y' S = (C+x'y')' Lan-Da Van DCD-04-6

Logic Diagram of 1-Bit Half Adder Lan-Da Van DCD-04-7

Full-Adder The arithmetic sum of three input bits three input bits x, y: two significant bits z: the carry bit from the previous lower significant bit Two output bits: C, S 1-Bit Full Adder Su m Carry Lan-Da Van DCD-04-8

Logic Diagram of 1-Bit Full Adder Lan-Da Van DCD-04-9

Logic Diagram of 1-Bit Full Adder S = x'y'z+x'yz'+ xy'z'+xyz = x (y z) +x(y z) = x y z C = xy + xz + yz = xy + xyz + xy z + xyz + x yz = xy + z (x y + xy) = xy + z (x y) Lan-Da Van DCD-04-10

Gate-level Modeling Bottom-up hierarchical description 11

Gate-level Modeling HDL Example 4.2 (cont.) S1 C1 C2 12

Gate-level Modeling Statement of Three-state gates: gate name (output, input, control); 13

Gate-level Modeling Example (gate instantiation with three-state gates) 14

Gate-level Modeling Nets (not a keyword): a set of data types representing connections between hardware elements wire, wor, wand, tri, supply1, supply0. 15

Dataflow Modeling What s the function? Example: assign Y = (A & S) (B & ~S) B m_out A select 16

Dataflow Modeling 17

Dataflow Modeling 18

Dataflow Modeling A Verilog HDL synthesis compiler can accept the module description as input, execute synthesis algorithms, and provide an output netlist and a schematic of a circuit equivalent to the one in Fig. 4.17 (see next page), all without manual intervention! 19

Magnitude Comparator Fig. 4.17 Four-bit magnitude comparator. 20

Magnitude Comparator The comparison of two numbers outputs: A>B, A=B, A<B Design Approaches the truth table 2 2n entries - too cumbersome for large n use inherent regularity of the problem reduce design efforts reduce human errors Algorithm -> logic A = A 3 A 2 A 1 A 0 ; B = B 3 B 2 B 1 B 0 A=B if A 3 =B 3, A 2 =B 2, A 1 =B 1 and A 0 =B 0 equality: x i = A i B i +A i 'B i ' (A=B) = x 3 x 2 x 1 x 0 (A>B) = A 3 B 3 '+x 3 A 2 B 2 '+x 3 x 2 A 1 B 1 '+x 3 x 2 x 1 A 0 B 0 ' (A<B) = A 3 'B 3 +x 3 A 2 'B 2 +x 3 x 2 A 1 'B 1 +x 3 x 2 x 1 A 0 'B 0 Implementation x i = (A i B i '+A i 'B i )' Lan-Da Van DCD-04-21

Dataflow Modeling Conditional operator (?:) condition? true-expression : false-expression B m_out A select 22

Behavioral Modeling If statement: if (select) OUT = A; B m_out A select 23

Behavioral Modeling 24

initial block Writing a Simple Test Bench Inputs specified by a three-bit truth table // #10: delayed by 10ns 25

Writing a Simple Test Bench Stimulus module 26

Writing a Simple Test Bench Interaction between stimulus and design modules 27

Writing a Simple Test Bench System tasks for display Syntax for $display, $write, and $monitor: Task-name (format specification, argument list); Example: Example: 28

Writing a Simple Test Bench B m_out A select 29

Writing a Simple Test Bench B m_out A select 30

Writing a Simple Test Bench a full adder 31

Writing a Simple Test Bench 32

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