EECS 3201: Digital Logic Design Lecture 4. Ihab Amer, PhD, SMIEEE, P.Eng.

Transcription

1 EECS 32: Digital Logic Design Lecture 4 Ihab Amer, PhD, SMIEEE, P.Eng.

2 What is a HDL? A high-level computer language that can describe digital systems in tetual form Two applications of HDL processing: Logic Simulation Logic Synthesis 2

3 HDL Applications Logic Simulation A simulator translates the HDL description to a readable output such as timing diagram It predicts how the hardware will work before it is actually fabricated Functional errors can be corrected before actual fabrication Stimulus that tests the design is called test-bench (also written in HDL) Logic Synthesis Deriving the gate-level netlist from the HDL Typically accompanied with optimization, and automated with computer software Restrictions on coding style for RTL model The outcome (netlist) is tool dependent 3

4 IEEE-Supported HDL s EECS 32 VHDL Verilog VHSIC HDL Based on Ada Department of defense (DARPA) mandated language Generally, considered more difficult to learn Verify Logic Based on C Started as a Gateway Design proprietary language then later bought by Cadence Generally, considered easier to learn 4

5 Eample (Simple Circuit) Module name Ports names module smpl_ct (A, B, C,, y); Punctuation Ports modes input A, B, C; output, y; wire e; Internal connection Gate output A B C smpl_ct y Primitive gates and g(e, A, B); not g2(y, C); or g3(, e, y); Gate inputs endmodule Optional gate-name 5

6 Gate Delays module ct_with_delay (A, B, C,, y); input A, B, C; output, y; wire e; and #(3) g(e, A, B); or #(2) g3(, e, y); not #() g2(y, C); endmodule Gate delay in (ns) Time (ns) Input A B C Output y e Delay = 3 ns Delay = 2 ns Delay = ns 6

7 Simulation Output Timing Diagram 7

8 Boolean Epression module ct_bln (A, B, C,, y); input A, B, C; output, y; OR Keyword endmodule assign = (A & B) ~C; AND NOT 8

9 Verilog HDL Operators Refer to table 4- of Mano tetbook for a list of Verilog HDL Operators 9

10 Three-State Gates Tri-state buffer if vs. if tri-state buffers if vs. if tri-state inverters

11 Four-Valued Logic Verilog Logic Values The underlying data representation allows for any bit to have one of four values:,, z (high impedance), and (unknown) No Question! - A possible output from tri-state gates - It is a real electric effect - Not a real value - Maybe,, z, or in the state of change - Simulator cannot determine the value, and perhaps you should worry!

12 2 Truth Tables for Primitive Gates z z and z z or z input output not z z or

13 Verilog Design Styles Verilog Design Styles Testbenches dataflow structural behavioral Continuous Assignment Components and interconnects E.g. Gate-level Modeling What is inside? Mostly Sequential circuits Registers State machines What happens inside? Subset most suitable for synthesis 3

14 Eample 2: MUX select select OUT B A OUT B A OUT = (A. select) + (B. select ) 4

15 Gate-Level Model module mu2_gl (A, B, select, OUT); Components and Interconnects input A, B, select; output OUT; wire s_comp, c, d; select s_comp endmodule not g(s_comp, select); and g2(c,select,a); and g3(d,s_comp,b); or g4(out,c,d); B A d c OUT 5

16 Dataflow Model module mu2_df (A, B, select, OUT); input A, B, select; output OUT; Continuous Assignment assign OUT = (A & select) (B & ~select); endmodule module mu2_df2 (A, B, select, OUT); input A, B, select; output OUT; Another Dataflow Model assign OUT = select? A : B; endmodule 6

17 Behavioral Model Mostly used with sequential circuits module mu2_bh (A, B, select, OUT); Retains its value until a new value is assigned endmodule input A, B, select; output OUT; reg OUT; (select or A or B) Sensitivity List if (select == ) OUT = A; else OUT = B; Procedural Assignment Equality Symbol Can be written as: if (select) Eecutes every time there is a change in any of the variables in the sensitivity list 7

18 Structural Design Recap Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions Components are interconnected in a hierarchical manner Structural descriptions may connect simple gates (gate-level) or comple, abstract components Useful when epressing a design that is naturally composed of sub-blocks 8

19 Data-Flow Design Recap Describes how data moves through the system and the various processing steps Data Flow uses series of continuous assignment statements Data Flow is most useful style when series of Boolean equations can represent a logic 9

20 Behavioral Design Recap It accurately models what happens on the inputs and outputs of the black bo (no matter what is inside and how it works) This style uses always statements in Verilog Procedural statements in an always block eecutes sequentially. However, the always block itself eecutes concurrently with other concurrent statements in the same module (instances, continuous assignments, and other always statements) Typically used for test-benches or high-level implementations to drive logic synthesis tools 2

21 Nets, Variables, Parameters, and Directives Net: Physical wire between modules A wire is the most commonly-used net Variable: Stores a value during a Verilog program s eecution, and needs not have physical significance in a circuit A reg is the most commonly-used variable Parameter: A facility provided by Verilog for defining named constants within a module, to improve readability and maintainability E.g. parameter ESC = 7 b; Directive: To control the compilation process include and define are the most commonly-used directives 2

22 Logical Vs Bitwise Operators Eamples of Ambiguities: (2 b && 2 b) Vs (2 b & 2 b)!(5) Vs ~(5) 22

23 Ok Design is done How should I test it? Same as what you would do to test a SW program: Give it some inputs, and see if it does what you epect After testing, do you guarantee that the program is bug free? NO! But, to the etent possible, you have determined that the program does what you want it to do Same happens in HW design, you simulate the system s behavior with some input stimulus 23

24 Test Bench Stimulus Module Design Module module testcircuit; reg TA, TB, Tselect; wire TOUT; module circuit (A, B, select, OUT); input A, B, select; output OUT; circuit cr (TA, TB, Tselect, TOUT); 24

25 I am sick of this MUX!! module stimcrct; reg A, B, select; Instance of design module wire OUT; mu2_df2 mu (A, B, select, OUT); initial Procedural Assignment begin used with reg A = 'b; B = 'b; select = 'b; # A = 'b; B = 'b; select = 'b; Eecutes only once at t = # $finish; end endmodule Terminates simulation Stimulus Module module mu2_df2 (A, B, select, OUT); input A, B, select; output OUT; assign OUT = select? A : B; endmodule Design Module 25

26 Simulation Output 26

27 Eamples of Stimulus Generation initial begin A = ; B = ; # A = ; #2 A = ; B = ; end initial begin D = 3 b; repeat (7) # D = D + 3 b; end 3-bits Truth Table 27

28 References Lecture Notes of Dr. Sebastian Magierowski Fall 23 Digital Design, 3 rd Edition, M. Morris, Mano Digital Design, 4 th Edition, John Wakerly cpk.auc.dk/education/ssu- 27/mm/ssu_mm.pdf /S/ 28