Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 33 Assembly Language Prof. Dr. Antônio Augusto Fröhlich guto@lisha.ufsc.br http://www.lisha.ufsc.br/~guto Sep 2006
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 34 Assembly Language Assembly language, commonly called assembly, asm or symbolic machine code, is a humanreadable notation for the machine language that a specific computer architecture uses. Machine language, a pattern of bits encoding machine operations, is made readable by replacing the raw values with symbols called mnemonics. (Wikipedia)
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 35 Assembler An assembler creates object code by translating assembly instruction mnemonics into opcodes, and by resolving symbolic names for memory locations and other entities. (David Salomon)
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 36 Memory Access Program instructions and data are stored in memory Must be brought into the CPU during execution Program instructions are automatically fetched by the CPU Control flow instructions guide the execution flow Data operands for ALU instructions are fetched by explicit instructions in the program Data access instructions
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 37 CPU Registers General Purpose Registers (GPR) Scratch storage Data Addresses Constants (0/1/ 1) Indexes for data structures Base/segment to segment memory Floating Point Registers (FPR) Floating point data
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 38 CPU Registers Control registers Program Counter (PC) / Instruction Pointer (IP) Points to the next instruction to be executed Flags ALU flags: carry, overflow, zero, etc Machine control flags: MMU, I/O, etc Stack pointer Top of the stack Frame pointer Return value/pointer
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 39 Data Addressing Modes Legend 16 bit architecture big endian byte addressed memory involved altered 102 104 106 108 Memory 10 20 30 40 Registers r1 10 r2 2 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 40 Data Addressing Modes Register Operand stored in a CPU register ALU operations Most used variables Automated by compilers 102 104 106 108 add r1, r2 (r1 < r1 + r2) Memory Registers 10 r1 10 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 41 Data Addressing Modes Register Operand stored in a CPU register ALU operations Most used variables Automated by compilers 102 104 106 108 add r1, r2 (r1 < r1 + r2) Memory Registers 10 r1 12 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 42 Data Addressing Modes Immediate Operand encoded along with operation Constants 102 104 106 108 add r1, #10 (r1 < r1 + 10) Memory Registers 10 r1 12 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 43 Data Addressing Modes Immediate Operand encoded along with operation Constants 102 104 106 108 add r1, #10 (r1 < r1 + 10) Memory Registers 10 r1 22 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 44 Data Addressing Modes Absolute Operand stored in memory at address Static data (static variables, class attributes) 102 104 106 108 add r1, (r1 < r1 + M[]) Memory Registers 10 r1 22 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 45 Data Addressing Modes Absolute Operand stored in memory at address Static data (static variables, class attributes) 102 104 106 108 add r1, (r1 < r1 + M[]) Memory Registers 10 r1 32 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 46 Data Addressing Modes Register Indirect Operand stored in a memory location pointed by a register Pointer deferring 102 104 106 108 add r1, (r3) (r1 < r1 + M[r3]) Memory Registers 10 r1 32 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 47 Data Addressing Modes Register Indirect Operand stored in a memory location pointed by a register Pointer deferring 102 104 106 108 add r1, (r3) (r1 < r1 + M[r3]) Memory Registers 10 r1 42 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 48 Data Addressing Modes Register Indirect with Displacement Operand stored in a memory location pointed by a register plus an offset Local variables (reg = frame pointer) 102 104 106 108 add r1, 4(r3) (r1 < r1 + M[r3 + 4]) Memory Registers 10 r1 42 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 49 Data Addressing Modes Register Indirect with Displacement Operand stored in a memory location pointed by a register plus an offset Local variables (reg = frame pointer) 102 104 106 108 add r1, 4(r3) (r1 < r1 + M[r3 + 4]) Memory Registers 10 r1 72 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 50 Data Addressing Modes Register Indirect Indexed Operand stored in a memory location pointed by an indexed register Array (reg1 = array, reg2 = index) 102 104 106 108 add r1, (r3, r2) (r1 < r1 + M[r3 + r2]) Memory Registers 10 r1 72 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 51 Data Addressing Modes Register Indirect Indexed Operand stored in a memory location pointed by an indexed register Array (reg1 = array, reg2 = index) 102 104 106 108 add r1, (r3, r2) (r1 < r1 + M[r3 + r2]) Memory Registers 10 r1 92 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 52 Data Addressing Modes Register Indirect with Post [Inc Dec]rement Operand stored in a memory location pointed by a register that is post [inc dec]remented Iteration (reg = array, inc = size of element ) 102 104 106 108 add r1, (r3)+ (r1 < r1 + M[r3]; r3 < r3 + s) Memory Registers 10 r1 92 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 53 Data Addressing Modes Register Indirect with Post [Inc Dec]rement Operand stored in a memory location pointed by a register that is post [inc dec]remented Iteration (reg = array, inc = size of element ) 102 104 106 108 add r1, (r3)+ (r1 < r1 + M[r3]; r3 < r3 + s) Memory Registers 10 r1 102 20 r2 30 2 40 r3 102
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 54 Data Addressing Modes Register Indirect with Pre [Inc Dec]rement Operand stored in a memory location pointed by a register that is pre [inc dec]remented Iteration Stack (reg = stack ptr) 102 104 106 108 add r1, (r3) (r3 < r3 s; r1 < r1 + M[r3]) Memory Registers 10 r1 102 20 r2 30 2 40 r3 102
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 55 Data Addressing Modes Register Indirect with Pre [Inc Dec]rement Operand stored in a memory location pointed by a register that is pre [inc dec]remented Iteration Stack (reg = stack ptr) 102 104 106 108 add r1, (r3) (r3 < r3 s; r1 < r1 + M[r3]) Memory Registers 10 r1 112 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 56 Data Addressing Modes Register Indirect Indexed and Scaled Operand stored in a memory location pointed by an indexed and scaled register Array (reg1 = array, reg2 = index, scale = size of element) add r1, (r3, r2, 2) 102 104 106 108 (r1 < r1 + M[r3 + r2 * 2) Memory Registers 10 r1 112 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 57 Data Addressing Modes Register Indirect Indexed and Scaled Operand stored in a memory location pointed by an indexed and scaled register Array (reg1 = array, reg2 = index, scale = size of element) add r1, (r3, r2, 2) 102 104 106 108 (r1 < r1 + M[r3 + r2 * 2) Memory Registers 10 r1 142 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 58 Data Addressing Modes Register Indirect with Displacement, Indexed and Scaled Array (dis = offeset, reg1 = array, reg2 = index, scale = size of element) add r1, 2(r3, r2, 2) 102 104 106 108 (r1 < r1 + M[r3 + 2 + r2 * 2]) Memory Registers 10 r1 142 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 59 Data Addressing Modes Register Indirect with Displacement, Indexed and Scaled Array (dis = offeset, reg1 = array, reg2 = index, scale = size of element) add r1, 2(r3, r2, 2) 102 104 106 108 (r1 < r1 + M[r3 + 2 + r2 * 2]) Memory Registers 10 r1 182 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 60 Data Addressing Modes Memory Indirect Operand stored in a memory location pointed by another memory localion Pointer to pointer deferring Call tables 102 104 106 108 add r1, @(r3) (r1 < r1 + M[M[r3]]) Memory Registers 106 r1 182 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 61 Data Addressing Modes Memory Indirect Operand stored in a memory location pointed by another memory localion Pointer to pointer deferring Call tables 102 104 106 108 add r1, @(r3) (r1 < r1 + M[M[r3]]) Memory Registers 106 r1 222 20 r2 30 2 40 r3
Sep 2006 Prof. Antônio Augusto Fröhlich (http://www.lisha.ufsc.br) 62 Data Addressing Modes Mode Example Meaning Register add r1, r2 r1 < r1 + r2 Immediate add r1, #10 r1 < r1 + 10 Absolute add r1, r1 < r1 + M[] Reg. Ind. Disp. add r1, (r3) r1 < r1 + M[r3] Reg. Ind. Disp. add r1, 4(r3) r1 < r1 + M[r3 + 4] Reg. Ind. Ind. add r1, (r3, r2) r1 < r1 + M[r3 + r2] Reg. Ind. Post add r1, (r3)+ r1 < r1 +M[r3]; r3 < r3 + s Reg. Ind. Pre add r1, (r3) r3 < r3 s; r1 < r1 +M[r3] Reg. Ind. Scal. add r1, (r3, r2, 2) r1 < r1 + M[r3 + r2 * 2] Reg. Ind. Disp. Scal. add r1, 2(r3, r2, 2) r1 < r1 + M[r3 +2 + r2 * 2] Memory Ind. add r1, @(r3) r1 < r1 + M[M[r3]]
Arithmetic and Logical Operations Hugo Marcondes hugom@lisha.ufsc.br http://www.lisha.ufsc.br/~hugom Sep 2006 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 1
Introduction Logical Operations Boolean Algebra AND, OR, NOR, XOR Shift Operations Shifts Right/Left Rotates Right/Left Arithmetic Operations Sum and Subtraction Multiplication and Division Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 2
Logical Operations Essential for low level programming Device Drivers Data Transmission (Serial/Parallel) Data Codification Cryptography Algorithms Bits are manipulated with bit masks Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 3
Logical Operations AND Function and rd, rs, rt Verify if a bit is set Unset a bit RD RS RT 0 0 0 0 0 1 0 1 0 1 1 1 Alternate form andi rd, rs, imm Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 4
Logical Operations OR Function or rd, rs, rt Set a bit Load constants RD RS RT 0 0 0 1 0 1 1 1 0 1 1 1 Alternate form ori rd, rs, imm Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 5
Logical Operations Negate OR Function nor rd, rs, rt Detect both zero bits Invert bits (all) RD RS RT 1 0 0 0 0 1 0 1 0 0 1 1 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 6
Logical Operations Exclusive OR Function xor rd, rs, rt Detect positions with different bits Invert bits (mask) RD RS RT 0 0 0 1 0 1 1 1 0 0 1 1 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 7
Logical Operations Left Shift Operations sll rd, rt, shamt Bit level Operations Multiplication and division Serialization / Parallelization [Kjell, 2004] Variable shift sllv rd, rt, rs Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 8
Logical Operations Right Shift Operations srl rd, rt, shamt Bit level Operations Multiplication and division Serialization / Parallelization Variable shift srlv rd, rt, rs Arithmetic shift sra rd, rt, shamt / srav rd, rt, rs [Kjell, 2004] Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 9
Logical Operations Right/Left Rotation Bits aren't discarded Right Rotation High bit moves to low Left Rotation Low bit moves high [Kjell, 2004] Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 10
Arithmetic Operations Sum With or without overflow signaling Can have a immediate operand Subtraction Sum of a negative number Overflow signalization Operation A B RES A + B >= 0 >= 0 < 0 A + B < 0 < 0 >= 0 A B >= 0 < 0 < 0 A B < 0 >= 0 >= 0 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 11
Arithmetic Operations Comparison Instructions Arithmetical comparison between number Less than, Greater Than, Equal, Not Equal The result of comparison can be in a general purpose register, or specific ones Intel: Flags register MIPS Set on Less Than slt rd, rs, rt / sltu rd, rs, rt slti rd, rs, imm / sltiu rd, rs, imm Pseudo instructions for other modes Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 12
Arithmetic Operation Multiplication Product of two N bits number is 2N bits 10 x 15 50 10 + 150 1010 x 1111 1010 1010 1010 1010 + 10110 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 13
Arithmetic Operation Result are stored on a double word register MIPS has HI and LO register Accessed mflo rd and mfhi rd instructions mult rs, rt and multu rs, rt HI 32 LO 32 < rs * rt Unsigned Multiplication Overflow don't occur Signed Multiplication Equal signs: positive result Can produce overflow MIPS need overflow detection on software Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 14
Arithmetic Operation Division div rs, rt and divu rs, rt LO < Quotient (rs/rt), HI < Remainder Mathematical Properties Don't generate overflow Raises a Zero Division exception Result is always unsigned Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 15
System Programming Flow Control Hugo Marcondes hugom@lisha.ufsc.br http://www.lisha.ufsc.br/~hugom Sep 2006 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 1
Introduction The power of computers is their ability to repeat actions and their ability to alter their operation depending on data Bradley Kjell Instruction Addressing Modes Branchs Conditional Unconditional Long Branch Jump Call Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 2
Instruction Addressing Modes Branch to an absolute address Concatenates imm with high bits of PC to complete address Calling near functions Absolute jump imm [n] PC < PC [w,n] : imm [n] w > word High Bit n > imm High Bit Memory Registers 0x80000004 PC 0x80000004 0x80000008 0x80000104 IMM 0x00000104... rs 9 0x80000108 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 3
Instruction Addressing Modes Branch to an absolute address Concatenates imm with high bits of PC to complete address Calling near functions Absolute jump imm [n] PC < PC [w,n] : imm [n] w > word High Bit n > imm High Bit Memory Registers 0x80000004 PC 0x80000104 0x80000008 0x80000104 IMM 0x00000104... rs 9 0x80000108 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 4
Instruction Addressing Modes Branch to a relative address Sum imm with the PC Usually imm is signed Code can be easily relocated Local Branch Relative Address branch imm PC < PC + imm Memory Registers 0x80000004 PC 0x80000004 0x80000008 0x80000104 0x80000108 IMM 0x00000104... rs 9 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 5
Instruction Addressing Modes Branch to a relative address Sum imm with the PC Usually imm is signed Code can be easily relocated Local Branch Relative Address branch imm PC < PC + imm Memory Registers 0x80000004 PC 0x80000108 0x80000008 0x80000104 0x80000108 IMM 0x00000104... rs 9 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 6
Instruction Addressing Modes Branch to an absolute address Contents of rs are transferred to PC Long Branch Register Indirect jump rs PC < rs Memory Registers 0x80000004 PC 0x80000004 0x80000008 0xC000000C IMM 0x00000104... rs 0xC0000010 0xC0000010 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 7
Instruction Addressing Modes Branch to an absolute address Contents of rs are transferred to PC Long Branch Register Indirect jump rs PC < rs Memory Registers 0x80000004 PC 0xC0000010 0x80000008 0xC000000C IMM 0x00000104... rs 0xC0000010 0xC0000010 Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 8
Branch Instructions Instructions used with address modes to change the execution flow of a program Conditional Branchs usually associated with Relative Addressing Mode Have a condition associated with the branch Comparison instructions/registers to express the condition Unconditional Branch Usually have all addressing mode forms Always change the execution flow Used in local context or for function call Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 9
Conditional Branch Condition expressed in the instruction beq rs, rt, LABEL (Branch Equal) PC < PC + LABEL, if rs == rt bne rs, rt, LABEL (Branch Not Equal) PC < PC + LABEL, if rs!= rt Condition resolved before the branch instruction slt rd, rs, rt (Set On Less Than) rd < 1, if rs < rt rd < 0, otherwise Used in conjunction with beq / bne Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 10
Unconditional Branch Are not associated with a condition b LABEL (Branch to LABEL Relative Address) PC < PC + LABEL j ADDR (Jump to ADDR Absolute Address) PC < PC : ADDR jr rs (Jump Register Register Indirect) PC < rs Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 11
Calls Branch the execution flow, but saves the return address The return address could be saved in stack or in a specific purpose register jal LABEL (Jump and Link Relative Address) RA < PC + 4 ; PC < PC : LABEL jalr rs (Jump and Link Register Register Indirect) RA < PC + 4 ; PC < RS Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 12
Programming Structures Exercise Write the assembler code that maps the following programming structure if ( a == 0 ) { // Block 1 } else { // Block 2 } while (a > 0) { //Block 3 a = a - 1; } Sep 2006 Hugo Marcondes (http://www.lisha.ufsc.br) 13