DATASHEET X24C45 256 Bit, 16 x 16 Bit Serial AUTOSTORE NOVRAM FN8104 Rev 0.00 FEATURES AUTOSTORE NOVRAM Automatically performs a store operation upon loss of V CC Single 5V supply Ideal for use with single chip microcomputers Minimum I/O interface Serial port compatible (COPS, 8051) Easily interfaced to microcontroller ports Software and hardware control of nonvolatile functions Auto recall on power-up TTL and CMOS compatible Low power dissipation Active current: 10mA Standby current: 50µA 8-lead PDIP and 8-lead SOIC packages High reliability Store cycles: 1,000,000 data retention: 100 years DESCRIPTION The Intersil X24C45 is a serial 256-bit NOVRAM featuring a static RAM configured 16 x 16, overlaid bit-by-bit with a nonvolatile EEPROM array. The X24C45 is fabricated with Intersil s Advanced CMOS Floating Gate technology. The Intersil NOVRAM design allows data to be transferred between the two memory arrays by means of software commands or external hardware inputs. A store operation (RAM data to EEPROM) is completed in 5ms or less and a recall operation (EEPROM data to RAM) is completed in 2µs or less. The X24C45 also includes the AUTOSTORE feature, a user selectable feature that automatically performs a store operation when V CC falls below a preset threshold. Intersil NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from EEPROM and a minimum 1,000,000 store operations. Inherent data retention is specified to be greater than 100 years. IBLOCK DIAGRAM Nonvolatile EEPROM STORE Row Decode Static RAM 256-Bit RECALL Control Logic RECALL (6) AS (7) CE (1) DI (3) SK (2) Instruction Register Column Decode DO (4) Instruction Decode 4-Bit Counter FN8104 Rev 0.00 Page 1 of 12
PIN DESCRIPTIONS Chip Enable (CE) The Chip Enable input must be HIGH to enable all read/write operations. CE must remain HIGH following a Read or Write command until the data transfer is complete. CE LOW places the X24C45 in the low power standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an operation in order to reset the instruction register in preparation for the next command. Serial Clock (SK) The Serial Clock input is used to clock all data into and out of the device. Data In (DI) Data In is the serial data input. Data Out (DO) Data Out is the serial data output. It is in the high impedance state except during data output cycles in response to a READ instruction. PIN CONFIGURATION DIP/SOIC CE 1 8 V CC SK 2 7 AS X24C45 DI 3 6 RECALL DO 4 5 V SS PIN NAMES Symbol Description CE Chip Enable SK Serial Clock DI Serial Data In DO Serial Data Out RECALL Recall Input AS AUTOSTORE Oput V CC +5V V SS Ground AUTOSTORE Output (AS) AS is an open drain output which, when asserted indicates V CC has fallen below the AUTOSTORE threshold (V ASTH ). AS may be wire-ored with multiple open drain outputs and used as an interrupt input to a microcontroller or as an input to a low power reset circuit. RECALL RECALL LOW will initiate an internal transfer of data from EEPROM to the RAM array. FN8104 Rev 0.00 Page 2 of 12
DEVICE OPERATION The X24C45 contains an 8-bit instruction register. It is accessed via the DI input, with data being clocked in on the rising edge of SK. CE must be HIGH during the entire data transfer operation. Table 1. contains a list of the instructions and their operation codes. The most significant bit (MSB) of all instructions is a logic one (HIGH), bits 6 through 3 are either RAM address bits (A) or don t cares (X) and bits 2 through 0 are the operation codes. The X24C45 requires the instruction to be shifted in with the MSB first. After CE is HIGH, the X24C45 will not begin to interpret the data stream until a logic "1" has been shifted in on DI. Therefore, CE may be brought HIGH with SK running and DI LOW. DI must then go HIGH to indicate the start condition of an instruction before the X24C45 will begin any action. In addition, the SK clock is totally static. The user can completely stop the clock and data shifting will be stopped. Restarting the clock will resume shifting of data. RCL and RECALL Either a software RCL instruction or a LOW on the RECALL input will initiate a transfer of EEPROM data into RAM. This software or hardware recall operation sets an internal "previous recall" latch. This latch is reset upon power-up and must be intentionally set by the user to enable any write or store operations. Although a recall operation is performed upon power-up, the previous recall latch is not set by this operation. WRDS and WREN Internally the X24C45 contains a "write enable" latch. This latch must be set for either writes to the RAM or store operations to the EEPROM. The WREN instruction sets the latch and the WRDS instruction resets the latch, disabling both RAM writes and EEPROM stores, effectively protecting the nonvolatile data from corruption. The write enable latch is automatically reset on powerup. STO The software STO instruction will initiate a transfer of data from RAM to EEPROM. In order to safeguard against unwanted store operations, the following conditions must be true: STO instruction issued. The internal "write enable" latch must be set (WREN instruction issued). The "previous recall" latch must be set (either a software or hardware recall operation). Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle, the write enable latch is reset. Refer to Figure 4 for a state diagram description of enabling/disabling conditions for store operations. Table 1. Instruction Set Instruction Format, I 2 I 1 I 0 Operation WRDS (Figure 3) 1XXXX000 Reset Write Enable Latch (Disables Writes and Stores) STO (Figure 3) 1XXXX001 STORE RAM Data in EEPROM ENAS 1XXXX010 Enable AUTOSTORE Feature WRITE (Figure 2) 1AAAA011 Write Data into RAM Address AAAA WREN (Figure 3) 1XXXX100 Set Write Enable Latch (Enables Writes and Stores) RCL (Figure 3) 1XXXX101 Recall EEPROM Data into RAM READ (Figure 1) 1AAAA11X Read Data from RAM Address AAAA FN8104 Rev 0.00 Page 3 of 12
WRITE The WRITE instruction contains the 4-bit address of the word to be written. The write instruction is immediately followed by the 16-bit word to be written. CE must remain HIGH during the entire operation. CE must go LOW before the next rising edge of SK. If CE is brought LOW prematurely (after the instruction but before 16 bits of data are transferred), the instruction register will be reset and the data that was shifted-in will be written to RAM. If CE is kept HIGH for more than 24 SK clock cycles (8-bit instruction plus 16-bit data), the data already shifted-in will be overwritten. READ The READ instruction contains the 4-bit address of the word to be accessed. Unlike the other six instructions, I 0 of the instruction word is a "don t care". This provides two advantages. In a design that ties both DI and DO together, the absence of an eighth bit in the instruction allows the host time to convert an I/O line from an output to an input. Secondly, it allows for valid data output during the ninth SK clock cycle. D0, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge of the eighth SK clock; whereas, all succeeding bits are clocked by the rising edge of SK (refer to Read Cycle Diagram). LOW POWER MODE When CE is LOW, non-critical internal devices are powered-down, placing the device in the standby power mode, thereby minimizing power consumption. AUTOSTORE Feature The AUTOSTORE instruction (ENAS) sets the "AUTO- STORE enable" latch, allowing the X24C45 to automatically perform a store operation when V CC falls below the AUTOSTORE threshold (V ASTH ). Notes: X = Don't Care A = Address WRITE PROTECTION The X24C45 provides two software write protection mechanisms to prevent inadvertent stores of unknown data. Power-Up Condition Upon power-up the "write enable" and "AUTOSTORE enable" latches are in the reset state, disabling any store operation. Unknown Data Store The "previous recall" latch must be set after power-up. It may be set only by performing a software or hardware recall operation, which assures that data in all RAM locations is valid. SYSTEM CONSIDERATIONS Power-Up Recall The X24C45 performs a power-up recall that transfers the EEPROM contents to the RAM array. Although the data may be read from the RAM array, this recall does not set the "previous recall" latch. During this power-up recall operation, all commands are ignored. Therefore, the host should delay any operations with the X24C45 a minimum of t PUR after V CC is stable. FN8104 Rev 0.00 Page 4 of 12
Figure 1. RAM Read CE SK 1 2 3 4 5 6 7 8 9 10 11 12 22 23 24 DI 1 A A A A 1 1 X* DO HIGH Z D 0 D 1 D 2 D 3 D 13 D 14 D 15 D 0 *Bit 8 of Read Instructions is Don t Care Figure 2. RAM Write CE SK 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 DI 1 A A A A 0 1 1 D 0 D 1 D 2 D 12 D 13 D 14 D 15 Figure 3. Non-Data Operations CE SK 1 2 3 4 5 6 7 8 DI 1 X X X X I 2 I 1 I 0 FN8104 Rev 0.00 Page 5 of 12
Figure 4. FX24C45 State Diagram Power On Power-Up Recall Power OFF RAM Read Enabled RAM Read AUTOSTORE Power-down STO Or Wrds Cmd RAM Read Enabled RCL Command Or Recall RAM Read RAM Read Or Write WREN Command RAM Read & Write Enabled Store Enabled AUTOSTORE Enabled ENAS Command STO Or Wrds Cmd RAM Read & Write Enabled Store Enabled WREN Command RAM Read Or Write FN8104 Rev 0.00 Page 6 of 12
ABSOLUTE MAXIMUM RATINGS Temperature under bias... -65 C to +135 C Storage temperature... -65 C to +150 C Voltage on any pin with respect to V SS... -1V to +7V D.C. output current...5ma Lead temperature (soldering, 10 seconds)... 300 C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Max. Commercial 0 C +70 C Industrial -40 C +85 C Military -55 C +125 C Supply Voltage Limits X24C45 5V ±10% D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Symbol Parameter Min. Limits Max. Unit Test Conditions l CC1 V CC supply current (TTL inputs) 10 ma SK = 0.4V/2.4V Levels @ 1MHz, DO = open, All other inputs = V IH l CC2 V CC supply current (during AUTOSTORE) 2 ma All inputs = V IH, CE = V IL DO = open, V CC = 4.3V I SB1 V CC standby current (TTL inputs) 1 ma DO = Open, CE = V IL, All other inputs = V IH I SB2 V CC standby current (CMOS inputs) 50 µa DO = Open, CE = V SS, All other inputs = V CC 0.3V I LI Input load current 10 µa V IN = V SS to V CC I LO Output leakage current 10 µa V OUT = V SS to V CC V (1) ll Input LOW voltage -1 0.8 V V (1) IH Input HIGH voltage 2 V CC + 1 V V OL Output LOW voltage 0.4 V I OL = 4.2mA V OH Output HIGH voltage 2.4 V I OH = 2mA V OL(AS) Output LOW voltage (AS) 0.4 V I OL(AS) = 1mA ENDURANCE AND DATA RETENTION Parameter Min. Unit Endurance 100,000 Data changes per bit Store cycles 1,000,000 Store cycles Data retention 100 Years CAPACITANCE T A = +25 C, f = 1MHz, V CC = 5V Symbol Parameter Max. Unit Test Conditions C (2) OUT Output capacitance 8 pf V OUT = 0V C (2) IN Input capacitance 6 pf V IN = 0V Notes: (1) V IL min. and V IH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. FN8104 Rev 0.00 Page 7 of 12
EQUIVALENT A.C. LOAD CIRCUIT 5V 919 A.C. CONDITIONS OF TEST Input pulse levels 0V to 3V Input rise and fall times 10ns Input and output timing levels 1.5V Output 497 100pF A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read and Write Cycle Limits Symbol Parameter Min. Max. Unit F (3) SK SK frequency 1 MHz t SKH SK positive pulse width 400 ns t SKL SK negative pulse width 400 ns t DS Data setup time 400 ns t DH Data hold time 80 ns t PD1 SK to data bit 0 valid 375 ns t PD SK to data valid 375 ns t Z Chip enable to output high Z 1 µs t CES Chip enable setup 800 ns t CEH Chip enable hold 350 ns t CDS Chip deselect 800 ns POWER-UP TIMING Symbol Parameter Max. Unit t (4) PUR Power-up to read operation 200 µs t (4) PUW Power-up to write or store operation 5 ms Notes: (3) SK rise and fall times must be less than 50ns. (4) t PUR and t PUW are the delays required from the time V CC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested. FN8104 Rev 0.00 Page 8 of 12
Write Cycle SK CYCLE # t SKH 1/F SK t SKL SK x 1 2 n t CES t CEH t CDS CE t DS t DH DI Read Cycle SK CYCLE # SK 6 7 8 9 10 n V IH CE t PD DI I2 I1 DON T CARE t PD1 t Z DO High Z D0 D1 Dn High Z FN8104 Rev 0.00 Page 9 of 12
NONVOLATILE OPERATIONS Operation RECALL Software Instruction Write Enable Latch State Previous Recall Latch State Hardware recall 0 NOP (5) X X Software recall 1 RCL X X Software store 1 STO SET SET ARRAY RECALL LIMITS Symbol Parameter Min. Max. Unit t RCC Recall cycle time 2 µs t RCP Recall pulse width (6) 500 ns t RCZ Recall to output in high Z 500 ns Recall Timing t RCC RECALL t RCP DO t RCZ High Z SOFTWARE STORE CYCLE LIMITS Symbol Parameter Min. Typ. (7) Max. Unit t ST Store time after clock 8 of STO command 2 5 ms Notes: (5) NOP designates when the X24C45 is not currently executing an instruction. (6) RECALL rise time must be <10µs. (7) Typical values are for T A = 25 C and nominal supply voltage. FN8104 Rev 0.00 Page 10 of 12
AUTOSTORE CYCLE LIMITS Symbol Parameter Min. Max. Unit t ASTO AUTOSTORE cycle time 5 ms V ASTH AUTOSTORE threshold voltage 4.0 4.3 V V ASEND AUTOSTORE cycle end voltage 3.5 V AUTOSTORE Cycle Timing Diagrams 5 V CC Volts (V) 4 3 2 AUTOSTORE Cycle in Progress V ASTH V ASEND 1 Store Time t ASTO Time (ms) V CC V ASTH 0V t PUR t ASTO t PUR AS SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don t Care: Changes Allowed N/A Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance FN8104 Rev 0.00 Page 11 of 12
Ordering Information X24C45 P T -V Device V CC Limits Blank = 5V ± 10% Temperature Range Blank = Commercial = 0 C to +70 C I = Industrial = -40 C to +85 C M = Military = -55 C to +125 C Package P = 8-Lead Plastic DIP S = 8-Lead SOIC Copyright Intersil Americas LLC 2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8104 Rev 0.00 Page 12 of 12