VLSI-Design of Non-Volatile Memories Bearbeitet von Giovanni Campardo, Rino Micheloni, David Novosel 1. Auflage 2005. Buch. xxviii, 582 S. Hardcover ISBN 978 3 540 20198 4 Format (B x L): 15,5 x 23,5 cm Gewicht: 2270 g Weitere Fachgebiete > Technik > Elektronik > Halb- und Supraleitertechnologie schnell und portofrei erhältlich bei Die Online-Fachbuchhandlung beck-shop.de ist spezialisiert auf Fachbücher, insbesondere Recht, Steuern und Wirtschaft. Im Sortiment finden Sie alle Medien (Bücher, Zeitschriften, CDs, ebooks, etc.) aller Verlage. Ergänzt wird das Programm durch Services wie Neuerscheinungsdienst oder Zusammenstellungen von Büchern zu Sonderpreisen. Der Shop führt mehr als 8 Millionen Produkte.
Contents Foreword: Non-Volatile Memory Technology Evolution...XVII Systems Needs for Non-Volatile Storage...XVIII NOR Flash Memory... XXI NAND Flash Memory...XXIII New Memory Concepts...XXV Conclusions...XXVIII 1 Non-Volatile Memory Design... 1 1.1 Introduction... 1 1.2 Main Features of Non-Volatile Memories... 2 1.3 Program... 3 1.4 Erase... 4 1.5 Distributions and Cycles... 4 1.6 Read Mode Architecture... 7 1.7 Write Mode Architecture... 8 1.8 Erase Mode Architecture... 9 1.9 Elements of Reliability... 10 1.10 Influence of Temperature and Supply Voltage... 10 1.11 Lab Activities... 11 1.12 Working Tools... 12 1.13 Shmoo Plots... 14 1.14 Testing... 16 1.15 Memory Pins Description... 16 Bibliography... 19 2 Process Aspects... 21 2.1 Introduction... 21 2.2 Main Steps of Fabrication for a CMOS Process... 21 Bibliography... 33 3 The MOSFET Transistor and the Memory Cell... 35 3.1 The MOSFET Transistor... 35 3.2 Transistors Available... 39 3.3 The Memory Cell... 44 3.4. Reading Characteristics... 48 3.5 Programming... 50 3.6 Program Algorithm... 57
X Contents 3.7 Erase Operation... 59 3.7.1 Erasing at Constant Voltage... 63 3.7.2 Constant Current Erase... 66 3.7.3 Erasing at Negative Gate and Triple-Well Array... 67 3.8 Erase Algorithm... 68 Bibliography... 69 4 Passive Components... 71 4.1 MOS Capacitors... 71 4.2 CMOS Technology Capacitors... 73 4.3 Integrated Resistors... 76 Bibliography... 79 5 Fundamental Circuit Blocks... 81 5.1 Introduction... 81 5.2 NMOS and CMOS Inverters... 81 5.3 The Cascode... 87 5.4 Differential Stage... 90 5.5 The Source Follower... 94 5.6 Voltage References... 96 5.6.1 NMOS... 97 5.6.2 CMOS... 100 5.6.3 Self-Biased Generator... 100 5.6.4 Band-Gap Reference... 102 5.7 Current Mirrors... 106 5.8 NMOS and CMOS Schmitt Trigger... 109 5.9 Voltage Level Shifter Latch... 114 5.10 Power On Reset Circuits... 115 5.11 Analog Switch... 119 5.12 Bootstrap... 123 5.12.1 PUSH-PULL Bootstrap... 129 5.12.2 PUSH-PULL Bootstrap with Anti-Glitch... 129 5.12.3 PUSH-PULL Bootstrap for a Large Load... 130 5.13 Oscillators... 131 5.14 Circuits to Detect Third Level Signals... 135 5.15 VDD Low Detector... 137 Bibliography... 138 6 Layout... 141 6.1 Custom Layout...141 6.2 A Three-Inputs NAND... 141 6.3 A Three-Inputs NOR... 144 6.4 An Interdigitized Inverter and a Capacitor... 144 6.5 Area and Perimeter Parasitic Capacitances...146 6.6 Automatic Layout... 147 Bibliography... 149
Contents XI 7 The Organization of the Memory Array...151 7.1 Introduction: EPROM Memories... 151 7.2 Flash Memory Organization: The Sectors... 151 7.3 An Array of Sectors... 158 7.4 Other Types of Array...159 7.4.1 DINOR Arrays (Divided Bit Line NOR)... 160 7.4.2 AND Arrays...162 7.4.3 NAND Architecture... 163 Bibliography... 165 8 The Input Buffer... 167 8.1 A Discussion on Input and Output Levels... 167 8.2 Input Buffers... 168 8.3 Examples of Input Buffers... 170 8.4 Automatic Stand-By Mode... 172 Bibliography... 174 9 Decoders... 175 9.1 Introduction... 175 9.2 Word Line Capacitance and Resistance... 179 9.3 Row Decoders... 184 9.4 NMOS Row Decoder... 190 9.5 CMOS Row Decoders... 195 9.6 A Dynamic CMOS Row Decoding... 195 9.7 A Semistatic CMOS Row Decoder... 197 9.8 Row Decoders for Low Supply Voltage... 199 9.9 Row Pre-Decoder at High Voltage... 202 9.10 Sector Decoding... 203 9.11 Memory Space for Test: the OTP Rows... 205 9.12 Hierarchical Row Decoding... 206 9.12.1 Read & Program... 207 9.12.2 Erase... 208 9.13 Low Switching ConsumptionRow Decoder... 211 9.14 Column Decoders... 213 Bibliography... 215 10 Boost... 217 10.1 Introduction... 217 10.2 Boost Techniques... 217 10.3 One-Shot Local Boost... 220 10.4 Double-BoostRow Decoder... 224 10.5 The Issue of the Recharge ofc BOOST... 227 10.6 Double-Path Boost Circuitry... 230 10.7 Boosted Voltages Switch... 233 10.8 Leakage Recovery Circuits... 236 Bibliography... 238
XII Contents 11 Synchronization Circuits... 239 11.1 ATD... 239 11.2 Multiple ATD Management... 241 11.3 Let s Connect the ATD to the Boost Circuitry... 243 11.4 Equalization of the Sense Amplifier: SAEQ...245 11.4.1 Word Line Overvoltage: One Shot Boost... 247 11.4.2 Word Line Overvoltage: Charge Pump... 248 11.5 The ENDREAD Signal... 250 11.6 The Cells Used by the Dummy Sense Amplifiers... 252 11.7 ATD ENDREAD Overlap... 252 11.8 Sequential Reads... 253 11.8.1 Asynchronous Page Mode... 255 11.8.2 The Synchronous Burst Mode... 257 Bibliography... 267 12 Reading Circuits... 269 12.1 The Inverter Approach... 269 12.2 Differential Read with Unbalanced Load... 273 12.3 Differential Reading with Current Offset... 277 12.4 Semi-Parallel Reference Current... 279 12.5 Techniques to Speed Up Read... 283 12.5.1 Equalization... 283 12.5.2 Precharge... 286 12.5.3 Clamping of the MAT and REF Nodes... 286 12.6 Differential Read with Current Mirror... 287 12.7 The Flash Cell... 289 12.8 Reading at Low VDD... 290 12.9 Amplified I/V Converter... 293 12.10 Amplified Semi-Parallel Reference... 294 12.11 Sizing of the Main Mirror... 296 12.12 Dynamic Analysis of the Sense Amplifier... 298 12.13 Precharge of the Output Stage of the Comparator... 301 12.14 Issues of the Reference... 302 12.14.1 EPROM-Like Reference... 302 12.14.2 Mini-Matrix... 303 12.15 Mirrored Reference Current... 304 12.16 The Verify Operation... 306 12.16.1 Erase... 306 12.16.2 Program... 308 Bibliography... 309 13 Multilevel Read... 313 13.1 Multilevel Storage... 313 13.2 Current Sensing Method... 315 13.3 Multilevel Programming... 318 13.4 Current/Voltage Reference Network... 319 13.5 Voltage Sensing Method... 322
Contents XIII 13.6 Sample & Hold Sense Amplifier... 325 13.7 Closed-Loop Voltage Sensing... 329 13.8 Hierarchical Row Decoding for Multiple Sensing Loops... 332 13.9 A/D Conversion... 335 13.10 Low Power Comparator... 338 Bibliography... 340 14 Program and Erase Algorithms... 343 14.1 Memory Architecture from the Program-Erase Functionality Point of View... 343 14.2 User Command to Program and Erase... 346 14.3 Program Algorithm for Bi-Level Memories... 347 14.4 Program Algorithm for Multilevel Memories... 351 14.5 Erase Algorithm... 356 14.6 Test Algorithms... 359 Bibliography... 360 15 Circuits Used in Program and Erase Operations... 361 15.1 Introduction... 361 15.2 Dual Voltage Devices... 362 15.3 Charge Pumps... 364 15.4 Different Types of Charge Pumps... 370 15.4.1 Dickson Pump Based on Bipolar Diodes... 371 15.4.2 Dickson Pump Based on Transistor-Based Diodes... 371 15.4.3 Charge Pump Based on Pass Transistors... 373 15.4.4 Voltage Doubler... 376 15.4.5 Voltage Tripler... 379 15.5 High Voltage Limiter... 381 15.6 Charge Pumps for Negative Voltages... 383 15.7 Voltage Regulation Principles... 384 15.8 Gate Voltage Regulation... 384 15.8.1 Circuit Structure... 384 15.8.2 Frequency Compensation... 388 15.8.3 Positive Power Supply Rejection Ratio (PSRR)... 396 15.8.4 Program Gate Voltage... 397 15.9 Drain Voltage Regulation and Temperature Dependence... 401 Bibliography... 406 16 High-Voltage ManagementSystem... 409 16.1 Introduction... 409 16.2 Sectors Biasing... 409 16.3 Local Sector Switch... 414 16.4 Stand-By Management... 417 16.5 High-Voltage Management... 423 16.5.1 Architecture Overview... 423 16.5.2 High-Voltage Read Path... 423 16.5.3 High-Voltage Program Path... 425
XIV Contents 16.5.4 High-Voltage Erase Path... 427 16.6 Modulation Effects... 429 16.6.1 Program Drain Voltage Modulation... 430 16.6.2 Body Voltage Modulation... 433 16.6.3 Source Voltage Modulation... 435 Bibliography... 440 17 Program and Erase Controller... 443 17.1 FSM Controller... 443 17.2 STD Cell Implementation of the FSM... 444 17.3 PLA Implementation of the FSM... 445 17.4 Microcontroller... 447 Bibliography... 454 18 Redundancy and Error Correction Codes... 455 18.1 Redundancy... 455 18.2 Redundancy & Read Path... 457 18.3 Yield... 459 18.4 UPROM Cells... 464 18.4.1 Read Circuitry for the UPROM Cells... 465 18.4.2 Supply Circuitry for the UPROM Cells... 467 18.5 The First Read After Power On Reset... 470 18.6 Error Correction Codes... 473 18.6.1 Elements of Coding Theory... 473 18.6.2 A Memory with ECC... 475 Bibliography... 478 19 The Output Buffer... 481 19.1 Introduction... 481 19.2 NMOS Output Buffer... 484 19.3 A CMOS Super Output Buffer... 485 19.4 The High Voltage Tolerance Issue... 488 19.5 Noise Induced on the Signal Circuitry by Commutation of the Output Buffers... 493 Bibliography... 501 20 Test Modes... 503 20.1 Introduction... 503 20.2 An Overview on Test Modes... 503 20.3 DMA Test... 505 20.4 Fast DMA... 507 20.5 Oxide Integrity Test... 507 Bibliography... 509 21 ESD & Latch-Up... 511 21.1 Notes on Bipolar Transistors... 511 21.2 Latch-Up... 516
Contents XV 21.3 Bipolar Transistors Used in Flash Memories... 518 21.4 Distribution of Power Supplies and ESD Protection Network... 520 Bibliography... 523 22 From Specification Analysis to Floorplan Definition... 525 22.1 Introduction... 525 22.2 Matrix Organization... 525 22.3 Matrix Row Dimensioning... 530 22.4 Dimensioning the Sectors... 533 22.5 Memory Configurations... 535 22.6 Organization of Column Decoding... 536 22.7 Redundancy... 538 22.8 First Considerations on Read Mode... 540 22.9 Architecture of the Reference... 542 22.10 Read Problems for a Non-Static Memory... 543 22.11 Erase and Program Circuits... 544 22.12 Pad Placement... 547 22.13 Control Logic and Related Circuitry... 549 Bibliography... 550 23 Photoalbum... 551 23.1 Introduction... 551 23.2 Figures Index... 551 23.3 The Photos... 552 Subject Index... 575