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Serial : 1. JP_EE_Microprocessor_130618 CLASS TEST Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 011-45124612 ELECTRICAL ENGINEERING Microprocessor Duration: 1.00 hr. Maximum Marks: 50 Read the following instructions carefully 1. This question paper contains 30 objective questions. Q.1-10 carry one mark each and Q.11-30 carry two marks each. 2. Answer all the questions. 3. Questions must be answered on Objective Response Sheet (ORS) by darkening the appropriate bubble (marked A, B, C, D) using HB pencil against the question number. Each question has only one correct answer. In case you wish to change an answer, erase the old answer completely using a good soft eraser. 4. There will be NEGATIVE marking. For each wrong answer 1/3rd of the full marks of the question will be deducted. More than one answer marked against a question will be deemed as an incorrect response and will be negatively marked. 5. Write your name & Roll No. at the specified locations on the right half of the ORS. 6. Using HB pencil, darken the appropriate bubble under each digit of your registration number. 7. No charts or tables will be provided in the examination hall. 8. Use the blank pages given for rough work. 9. Choose the Closest numerical answer among the choices given. DO NOT OPEN THIS TEST BOOKLET UNTIL YOU ARE ASKED TO DO SO

2 Electrical Engineering Q. No. 1 to Q. No. 10 carry 1 mark each Q.1 The status of carry flag and auxiliary carry flag of PSW register after executing the below code is MVI A, F1 H MVI B, 0F H ADD B (a) 0 and 0 (b) 1 and 1 (c) 0 and 1 (d) 1 and 0 Q.2 After executing the instruction XRA A (a) Carry, Auxiliary flags are set and Zero flag is set (b) Carry, Auxiliary flags are reset and Zero flag is set. (c) Carry flag is reset, Auxiliary flag is set and Zero flag is set. (d) Carry flag is set, Auxiliary flag is reset and Zero flag is set. Q.3 Which of the below listed instruction is direct addressing instruction? (a) MOV A,B (b) MVI B, OAH (c) MOV C,M (d) STA Address Q.4 A memory organisation of a computer consists of four 128 8 RAM chips and 512 8 ROM chip. How many address lines are required to access memory? (a) 7 (b) 9 (c) 22 (d) 16 Q.5 In the 8085 microprocessor, the RST 7 instruction transfers the program execution to the following location: (a) 30 H (b) 24 H (c) 38 H (d) 60 H Q.6 An instruction cycle is the time in which, hardwired controller completes four functions. The correct sequence of these functions is: (a) Decode - execute - fetch - update (b) Fetch - update - decode - execute (c) Execute - decode - fetch - update (d) Fetch - decode - update - execute Q.7 Consider the following set of instructions of 8085 microprocessor. MVI A, 82 H XRA A JP DISPLAY DISPLAY : OUT PORT 1 HLT The contents in PORT 1, after execution of the above program will be (a) 00 H (b) FF H (c) 92 H (d) 11 H Q.8 Which of the following Assembly language instruction can be used to clear the lower four bits of the accumulator in 8085 microprocessor? (a) XRI 0F H (b) ANI F0 H (c) XRI F0 H (d) ANI 0F H Q.9 In an 8085 microprocessor, ALE signal is made high to (a) Enable the data bus to be used as low order address bus (b) To latch data D 0 D 7 from data bus (c) To disable data bus (d) To achieve all the functions listed above Q.10 Stack overflow causes (a) Hardware interrupt (b) Internal interrupt (c) software interrupt (d) External interrupt Q. No. 1 to Q. No. 10 carry 1 mark each Q.11 Specify the number of times the following loop will be executed. ORA A MVI B, 64H LOOP : DCR B JNC LOOP (a) 100 times (b) 99 times (c) times (d) 101 times Q.12 Specify the contents of accumulator when the following program is executed MVI A, C4 H ORA A RRC RAL RRC (a) 42 H (b) 62 H (c) 52 H (d) None of these

CT-2018 EE Microprocessor 3 Q.13 A 4K byte RAM is interfaced with 8085 microprocessor and chip selection logic is given as CS = A 15 A 14 A 13 A 12 The memory range interfaced is (a) 5000H- 5FFFH (b) 6000H - 6FFFH (c) 4000H - 4FFFH (d) 3000H - 3FFFH Q.14 The content of HL pair and stack pointer is 0484 H and 2099 H respectively. The instruction DAD SP is executed. Content of HL pair and stack pointer after execution is respectively. (a) 2583 H, 2099 H (b) 251D H, 2099 H (c) 0484 H, 2099 H (d) 2099 H, 0484 H Q.15 A snapshot of the address, data and control buses of an 8085 microprocessor executing a program is given below. Address Data IO/M RD WR 2424 H 20 H Logic high Logic low Logic high The assembly language instruction being executed is (a) IN 24 H (b) IN 20 H (c) OUT 24 H (d) OUT 20 H Q.16 Match List-I (Interrupt) with List-II (Property) List-I List-II P. RST 7.5 1. Non-maskable Q. RST 6.5 2. Edge sensitive R. INTR 3. Level sensitive S. TRAP 4. Non-vectored Codes: P Q R S (a) 1 3 4 2 (b) 2 4 3 1 (c) 1 4 3 2 (d) 2 3 4 1 Q.17 Which of the following set of instruction are Machine Control Instructions? (a) HLT and NOP (b) CALL and RET (c) IN and OUT (d) CMP and ROTATE Q.18 An Intel 8085 processor is executing the program given below: MVI A, 10 H MVI B, 10 H BACK: NOP ADD B RLC JNC BACK HLT What is the number of times that the instruction NOP will be executed? (a) One (b) Two (c) Three (d) Four Q.19 A microprocessor using a 3 MHz clock has three T states in each machine cycle. If an instruction cycle needs 4 machine cycles (except opcode fetch), how much time will be taken to complete the execution of this instruction? (a) 4 µs (b) 1333 µs (c) 1 µs (d) 333 µs Q.20 The range of the address of the RAM which is interfaced to a microprocessor as shown in fig. is A 13 A 14 A 15 A 10 A 11 A 12 A B C (a) 1400-17FF (c) F000 - FFFF 3 8 decoder G Y 5 A 0 A 9 RAM CS (b) E400 - EFFF (d) F400 - F7FF Q.21 With a clock frequency of 3 MHz, the execution time for the instructions LDA addr and STA addr of 8085 will be respectively (a) 3975 ns, 3960 ns (b) 4333 ns, 3960 ns (c) 4333 ns, 4333 ns (d) 3975 ns, 3975 ns Q.22 When a processor uses handshaking, the following handshaking signals are present: 1. Acknowledge 2. Status 3. Strobe 4. Data transfer

4 Electrical Engineering What is the correct sequence in which the signal appear? (a) strobe - data transfer - acknowledge - status (b) strobe - status - data transfer - acknowledge (c) status - strobe - data transfer - acknowledge (d) status - data transfer - acknowledge - strobe Q.23 After the execution of the following program in the 8085 microprocessor, the contents of the accumulator and status of CY flag will be respectively: Address Code Mnemonics 203 A 3E20 MVI A, 20 H 203 C 2A 3A 20 LHLD 203 AH 203 F 86 ADD M 2040 76 HLT (a) 20 H, set (b) 40 H, reset (c) 3E H, reset (d) 8C H, set Q.24 Consider the following set of instructions to be executed by an 8085 microprocessor. The input port having an address of 01 H has the data 05 H. IN 01 H ANI 80 H After execution of the above two instructions, the contents of flag register will be D7 D6 D5 D4 D3 D2 D1 D0 (a) 1 0 1 1 0 (b) 0 1 0 1 0 (c) 0 1 1 1 0 (d) 0 1 1 0 0 Q.25 When RET instruction at the end of subroutine is executed, (a) the information where the stack is initialized is transferred to the stack pointer (b) the memory address of RET instruction is transferred to the program counter (c) the two data bytes stored in the top two locations of the stack are transferred to the program counter. (d) the two data bytes stored in the top two locations of the stack are transferred to the stack pointer. Q.26 The contents of some memory locations of an 8085 microprocessor based system are given as follows. Address Contents 3000 H 02 H 3001 H 30 H 3002 H 00 H 3003 H 30 H Consider the assembly language program given below LXI H, 3000 H MOV E, M INX H MOV D, M LDAX D MOV L, A INX D LDAX D MOV H, A NOP the contents of register H after execution of the above program will be (a) 00H (b) 02H (c) 03H (d) 30H Q.27 A RAM chip has capacity of 1024 words of 8 bits each (1 k 8). The number of 2 4 decoders with enable line needed to construct a 16 k 16 RAM using 1 k 8 RAM chips is (a) 4 (b) 5 (c) 6 (d) 7 Q.28 Consider the following assembly langulage program of an 8085 microprocessor. LHLD 3000 H XCHG LHLD 3002 H DAD D SHLD 3004 H HLT If the contents of 3000 H, 3001 H, 3002 H and 3003 H are 12 H, 04 H, 04 H and 03 H respectively, then the contents of the memory location 3004 H, after execution of the program will be (a) 04 H (b) 07 H (c) 16 H (d) 23 H Q.29 The decimal equivalent of the contents of the memory location 3000 H, after execution of the following assembly language program in an 8085 microprocessor is

CT-2018 EE Microprocessor 5 MVI B, 00 H MVI A, 1C H DCR B DAA STA 3000 H HLT (a) 22 (b) 27 (c) 34 (d) 39 Q.30 In an 8085 microprocessor, the accumulator contents are AAH. After executing the instruction CPI 99 H in the microprocessor, (a) carry flag will be set but zero flag will be reset. (b) both carry and zero flag will be reset (c) carry flag will be reset but, zero flag will be set. (d) both carry and zero flags will be set.

Serial : 1. JP_EE_Microprocessor_130618 Delhi Noida Bhopal Hyderabad Jaipur Lucknow Indore Pune Bhubaneswar Kolkata Patna Web: E-mail: info@madeeasy.in Ph: 011-45124612 CLASS TEST 2018-19 ELECTRICAL ENGINEERING Subject : Microprocessor Date of test : 13/06/2018 Answer Key 1. (b) 7. (a) 13. (d) 19. (a) 25. (c) 2. (b) 8. (b) 14. (b) 20. (d) 26. (d) 3. (d) 9. (a) 15. (a) 21. (c) 27. (b) 4. (d) 10. (b) 16. (d) 22. (b) 28. (c) 5. (c) 11. (c) 17. (a) 23. (b) 29. (c) 6. (b) 12. (b) 18. (c) 24. (c) 30. (b)

CT-2018 EE Microprocessor 7 Detailed Explanations 1. (b) PSW register can be seen as accumulator register with flag register. Status Register PSW = Accumulator + S Z X AC X P X CY contents of register B are added to register A and the result is stored in register A. Here the flags get affected as ADD is an arithmetic instruction. 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PSW = 0000000001X1X1X1 X is a don t care bit CY = 1 AC = 1 2. (b) When XRA instruction is executed Sign, Zero, Parity flags are modified to reflect the result of operation with Carry and Auxiliary flags being reset. 3. (d) Address itself is given so STA is direct addressing mode. 4. (d) For 128 8 RAM Chip, no. o f address lines required = 7 (128 = 2 7 ) For 512 8 ROM Chip, no. of address lines required = 9 (512 = 2 9 ) Hence, the total number of address lines required to access memory = 7 + 9 = 16 5. (c) Hexadecimal equivalent of (7 8 = 56) is 0038 H 38 H 16 16 56 3 8 0 3 6. (b) An instruction cycle consists of following steps. In step-1 : Code is fetched from memory In step-2 : Program counter is updated In step-3 : Instruction code is decoded In step-4 : Instruction is executed 7. (a) MVI A, 82 H : (A) 82 H XRA A : (A) 1000 0010 1000 0010 0000 0000 = 00 H JP DISPLAY : Jump if positive as sign flag = 0 after XRA A, condition for Jump is satisfied (Port 1) (A) (Port 1) = 00 H. 9. (a) When ALE goes high data bus is used as address bus when it goes low it is used as data bus only.

8 Electrical Engineering 10. (b) Stack overflow occurs while execution of a programme due to logical faults. So, it is a program dependent, hence interrupt is activated. 11. (c) ORA A CY = 0 to reset the carry MVI B, 64H B = (64) H = (100) 10 DCR B content of B is decreamented by 1. All the flags are affected except carry flag. So, conditional jump it not carry (CY = 0) will be true always and loop will be executed infinitely. 12. (b) Accumulator is initially loaded with C4 H. Instruction ORA A resets the carry flag RRC CY 1 1 0 0 0 1 0 0 0 CY 0 1 1 0 0 0 1 0 0 RAL CY 0 0 1 1 0 0 0 1 0 1 1 0 0 0 1 0 0 RRC 1 1 0 0 0 1 0 0 0 CY 0 1 1 0 0 0 1 0 0 CY Contents of accumulator are 62 H. 13. (d) Range : 3000H 3FFFH A 15 A 14 A 13 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 0 0 1 1 0 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 14. (b) HL 04 84 H SP 20 99 H DAD 25 1 D H Result of DAD instruction is stored in HL pair while the content of stack pointer remain unchanged. 15. (a) By analysing the given table I OM / is high IO operation RD is logic low IN operation In I/O mapped I/O both address lines i.e., lower order and higher order. Contains same address. IN 24 H is being executed.

CT-2018 EE Microprocessor 9 16. (d) TRAP Edge and level both RST 7.5 Edge trigger RST 6.5 Level trigger RST 6.5 Level trigger INTR Level trigger TRAP Vectored (0024) RST 7.5 Vectored (003C) RST 6.5 Vectored (0034) RST 5.5 Vectored (002C) INTR Non vectored TRAP Non maskable RST 7.5 Maskable RST 6.5 Maskable RST 6.5 Maskable INTR Maskable 17. (a) HLT and NOP are the machine control instructions. These instructions affect the operation of the processor. 18. (c) MVI A, 10 H ; Move data 10 H to A MVI B, 10 H ; Move data 10 H to register B. BACK: NOP ; No operation ADD B ; Adds contents of register B (i.e 10 H) to A(i.e 10 H) and store result in A 10 H : 00010000 + 10H : 00010000 00100000 A = 20 H and CY = 0 RLC ; Rotate contents of accumulator to left without carry flag Before rotation: CY = 0 0 0 1 0 0 0 0 0 0 After rotation: CY = 1 0 1 0 0 0 0 0 0 0 A = 40 H and CY = 0 JNC BACK ; Jumps to BACK if CY = 0 HLT ; Halts the execution After execution of RLC instruction 3 times, CY flag will be set. So, the instruction NOP will be executed three times in the given program.

10 Electrical Engineering 19. (a) Given, number of T-states in each machine cycle = 3 No. of T-states required in 4 machine cycles = 12 One T state is precisely equal to one time period of clock signal. So, time of one T-state is: T = 1 3 µ s Time of 12 T-state = 12 T = 1 12 = 4 µs 3 20. (d) For enabling the decoder, output of NAND should be low and output of NAND gate is low when the address lines A 13 to A 15 are high. And for generation of chip select signal the output line Y 5 of decoder should be selected. Line Y 5 is selected when address lines A 10 = 1. A 11 =0 and A 12 =1 So, for the selection of given RAM, A 10 =1, A 11 =0, A 12 =1, A 13 =1, A 14 =1, A 15 =1 Hence, address range will be as follows. A 15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 = F400 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 = F7FF Decoder enable Chip Select 21. (c) The instruction STA addr and LDA addr both requires 13 T-states. one T-states = one time period of clock signal. Time period of clock is: T = 1 3 µ s Time of 13 T-states = 13 3 = 4333 ns 22. (b) PUSH instruction is used to store contents of register pairs on top of stack is as under, PUSH R P R P BC, DE, HL & PSW It stores the contents of register pair R P on two top locations of stack It is a 1-byte instruction and uses register indirect addressing mode. Three machine cycles (OP + MW + MW) & 12 T-states are required. No flag is affected It is clear that it can t be used for storing the data of SP and PC on top of the stack.

CT-2018 EE Microprocessor 11 23. (b) 203A MVI A, 20 H ; content of A = 20 H 203C LHLD 203 A H ; The content of 203A H are loaded in L and content of 203B H are located in H. So, new contents of H and L will be L = 3E H and H = 20 H ADD M ; contents of memory location 203 E H (i.e 20 H from program) are added to A. A : 00100000 B : 00100000 001000000 So, A = 40 H and CY = 0 (Reset) HLT ; Halts the program execution. 24. (c) 05 H AND 80 H = 00 H After ANI instruction, CY = reset, AC is set and S, Z, P are modified. S = 0, Z = 1, AC = 1, P = 1, CY = 0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 X 1 X 1 X 0 S Z X AC X P X 25. (c) After the execution of RET instruction the top two bytes of stacks are transferred to program counter. 26. (d) LXI H, 3000 H HL : 3000 H MOV E, M E : 02 H INX H HL : 3001 H MOV D, M D : 30 H LDAX D A : 00 H MOV L, A L : 00 H INX D DE : 3003 H LDAX D A : 30 H MOV H, A H : 30 H After execution of the program contents of H = 30 H. 27. (b) RAM chip size = 1 k 8 (1024 words of 8 bits each) RAM to be constructed = 16 k 16 CY Number of chips required = 16 k 16 1k 8 = 16 2 16 chips vertically, each having 2 chips horizontally required. so, to select 16 chips vertically, we need 4 16 decoder, but available one is 2 4 decoder. to construct a 4 16 decoder using 2 4 decoder, 16 4 = 4 + = 1 4 4 = 5 2 4 decoders are required.

12 Electrical Engineering 28. (c) LHLD 3000 H : Load HL Pair will (L) (3000 H) (H) (3001 H) XCHG : Exchange HL with DE pair LHLD 3002 H : (L) (3002 H) (H) (3003 H) DAD D : Add DE pair with HL pair SHLD 3004 H : Store result in address location 3004 H (3004 H) (L) (3005 H) (H) Before Execution 3000 H : 12 H 3001 H : 04 H 3002 H : 04 H 3003 H : 03 H 0412 H + 0304 H = 0716 H After Execution 3004 H : 16 H 3005 H : 07 H contents of memory location 3004 H = 16 H. 29. (c) MVI B, 00 H : (B) 00 H MVI A, 1C H : (A) 1C H DCR B : (B) (B) 1 = FF H DAA : Adjust the accumulator to BCD values (A) =1C H 0 0 0 1 1 1 0 0 + 0 1 1 0 0 0 1 0 0 0 1 0 Hence (A) : 22 H Contents of 3000 H is 22 H 22 H = (16 2 + 2) 10 = (34) 10. 30. (b) Given, content of A = AAH CPI 99 H ; Compares the data 99H with content of A. The comparison is made by subtracting 99H from the contents of A(ie. AAH). The contents of A remains unaffected but status of result is reflected by flags. AA : 1010 1010 99H : 1001 1001 000010001 After comparison both zero flag and carry flag are reset.