PCIe on 3U and 6U CompactPCI Mark Wetzel Principal Engineer National Instruments

Agenda Overview of CompactPCI CompactPCI Express Development Connectors, Boards and Slots Backplane Examples CompactPCI Express Electricals Keying Summary Copyright 2005, PCI-SIG, All Rights Reserved 3

CompactPCI Specification maintained by the PICMG organization Brought PCI to the Eurocard modular form factor made popular by VME Base specification defines PCI and I/O pins Sub specifications define I/O pin usage Serves industrial, telecom, test, and mil-aero markets Copyright 2005, PCI-SIG, All Rights Reserved 4

CompactPCI Specifications and I/O pin Usage Spec Number PICMG 2.0 PICMG 2.1 PICMG 2.2 PICMG 2.3 PICMG 2.4 PICMG 2.5 PICMG 2.7 PICMG 2.9 PICMG 2.10 PICMG 2.11 PICMG 2.12 PICMG 2.14 PICMG 2.15 PICMG 2.16 PICMG 2.17 PICMG 2.18 PICMG 2.20 Spec Name Compact PCI Core Specification CompactPCI Hot Swap VME64x on CompactPCI PMC I/O Pin Assignments on CompactPCI IP I/O Pin Assignments on CompactPCI CompactPCI Computer Telephony CompactPCI 6U Dual System Slot Specification CompactPCI System Management Specification CompactPCI Keying of CompactPCI Board and Backplanes CompactPCI Power Interface CompactPCI Hot Swap Infrastructure Interface CompactPCI Multi Computing Specification CompactPCI PCI Telecom Mezzanine/Carrier Card (PTMC) CompactPCI Packet Switching Backplane CompactPCI StarFabric specification CompactPCI Serial RapidIO Specification CompactPCI Serial Mesh Backplane Specification Copyright 2005, PCI-SIG, All Rights Reserved 7

CompactPCI Express Development 45 Company PICMG subcommittee formed 4/2004 Major Goals: PCI Express to CompactPCI Provide in-system and in-slot compatibility with existing CompactPCI products Selected differential connectors Performed simulations Developed and tooled a new connector Wrote specification that includes detailed mechanical, electrical, and even connector specifications. Passed member review and currently in adoption ballot to be complete end of June Copyright 2005, PCI-SIG, All Rights Reserved 9

System Slot Link Capability 2 modes of operation depending on backplane routing 4 link mode (mandatory for controllers) Typically for direct connection to 3 or 4 slots 4 x4 links (each link could be x1 also) 2 link mode (optional for controllers) Typically for connection to fan out switches 2 links: 1 x16 & 1 x8 (each link could be smaller: x8, x4, or x1) Single controller design can support both LINKCAP pin on backplane used to set the mode Copyright 2005, PCI-SIG, All Rights Reserved 15

Slots That Provide Compatibility Legacy Slot: (In-System Compatibility) Defined exactly as a PICMG 2.0 (CompactPCI) slot Hybrid Slot: (In-Slot Compatibility) Has PCI and PCI Express Can plug in: 32 bit CompactPCI board Type 2 Peripheral Board Modified PXI Peripheral Module Copyright 2005, PCI-SIG, All Rights Reserved 18

Backplane Example: Chassis w/ Type 2 and Hybrid Slots 32-lane Switch System Slot x8 PCIe x8 PCIe x4 PCIe 16-lane Switch PCIe Switch x4 PCIe PCIe Switch x4 PCIe x4 PCIe x4 PCIe x4 PCIe x4 PCIe x4 PCIe PCI Bus Seg. 1 PCIe to PCI Bridge Hybrid Per. Slots Copyright 2005, PCI-SIG, All Rights Reserved 25

Compatibility Between Devices All devices must work as x1 x8 devices typically work as x4 Chassis suppliers choose how wide they route to boards System board designers choose how wide the links are that they provide Peripheral board designers choose the width they need Copyright 2005, PCI-SIG, All Rights Reserved 26

PCI Express Communication Signal Name ypetpx ypetnx yperpx ypernx yrefclk+ yrefclk- PERST# Description PCI Express Transmit Positive PCI Express Transmit Negative PCI Express Receive Positive PCI Express Receive Negative PCI Express 100MHz Positive PCI Express 100MHz Negative PCI Express Reset Copyright 2005, PCI-SIG, All Rights Reserved 29

Miscellaneous Sidebands Signal Name SMBDAT SMBCLK ALERT# SYSEN# GA4..GA0 WAKE# 5VAux Description SMBus Data SMBus Clock SMBus Interrupt Indicates if module is in system slot Geographical Addressing (must have registers) Request to bring system out of sleep 5V Standby power (available anytime PSU has AC) Copyright 2005, PCI-SIG, All Rights Reserved 30

Hot-Plug Signals Signal Name Description ATNLED Controls LED on board for Hot-Plug ATNSW# Indicates module is requesting Hot-Plug PRSNT# Indicates module is being removed/installed PWREN# Controls power supply on module for Hot-Plug MPWRGD# Indicates power supply on module is up Copyright 2005, PCI-SIG, All Rights Reserved 31

System Slot Specific Signals Signal Name Description PWR_OK Indicates PSU outputs are up PS_ON Controls power supply state LINKCAP Indicates System Slot Routing PWRBTN# Indicates PSU state change request Copyright 2005, PCI-SIG, All Rights Reserved 32

Electrical Requirements: Loss LOSS PARAMETER SYMBOL LOSS BUDGET VALUE AT 1.25 GHZ (DB) LOSS BUDGET VALUE AT 625 MHZ (DB) Total Loss L Total < 13.20 < 9.20 Guard band 1.00 0.60 PXIe Peripheral Module L PT L PR < 1.50 < 1.25 < 0.95 < 0.75 Backplane L B < 8.95 < 6.55 System Module L CT L CR < 2.00 < 1.75 < 1.30 < 1.10 Copyright 2005, PCI-SIG, All Rights Reserved 34

Electrical Requirements: Jitter JITTER PARAMETER PEAK-TO-PEAK JITTER BUDGET VALUE UI (PS) Type 1/2 Peripheral Board J AR < 0.0250 (10ps) J AT < 0.0325 (13ps) Backplane and Mated Connectors J B < 0.1675 (67ps) J B < 0.1675 (67ps) System Board/Switch Board J AT < 0.0325 (13ps) J AR < 0.0250 (10ps) Total Jitter J Total < 0.225 (90ps) Copyright 2005, PCI-SIG, All Rights Reserved 36

Peripheral Transmitter Compliance Eye Parameter Vtx A Vtx A _d Ttx A @ BER 10-12 Ttx A @ BER 10-6 Value at BER 10-12 >= 673mV >= 453mV >= 287ps >= 300ps Compliance Backplane Needed Vtx A Ttx A Vtx A _d Copyright 2005, PCI-SIG, All Rights Reserved 37

System Module Transmitter Compliance Eye Parameter Vtx A Vtx A _d Ttx A @ BER 10-12 Ttx A @ BER 10-6 Value at BER 10-12 >= 635mV >= 435mV >= 287ps >= 300ps Compliance Backplane Needed Vtx A Ttx A Vtx A _d Copyright 2005, PCI-SIG, All Rights Reserved 38

Peripheral and System Receive Compliance Eye Primarily for simulation Could use for validating traces 50 Ohm termination stuffed in place of silicon Ideal source on compliance board adjusted to be worse case at board under test PCIe specification compliance not guaranteed due to actual silicon non-ideal termination Copyright 2005, PCI-SIG, All Rights Reserved 39

Backplane Compliance Eye Parameter Vrx A Vrx A _d Trx A @ BER 10-12 Ttx A Vtx A Vtx A _d Value >= 299mV >= 276mV >= 343ps Compliance System Module connects to ARB to generate PCIe Compliance diagram Compliance Peripheral use to measure compliance eye Copyright 2005, PCI-SIG, All Rights Reserved 40

Lane to Lane skew SKEW PARAMETER SYMBOL SKEW VALUES Total Interconnect Skew S T 1.8 ns PXIe Peripheral Module S A 0.20 ns Backplane S B 1.00 ns System Module S C 0.4 ns Copyright 2005, PCI-SIG, All Rights Reserved 41

Crosstalk Backplane Eye Diagrams already assume a reasonable crosstalk level when link is active Need to ensure <65mV to ensure idle links are not incorrectly activated Copyright 2005, PCI-SIG, All Rights Reserved 43

Reference Clock LVPECL to the Peripheral Board DC Biased on Peripheral to be compliant with PCI Express Components Electrical and timing requirements specified Copyright 2005, PCI-SIG, All Rights Reserved 44

SMBus 2 Wire serial bus plus interrupt Main use is for chassis identification, chassis thermal management, and chassis health. May be used for Wake on Lan or remote management using ethernet peripheral module No use case for peripherals defined currently Capacitance budgets, strong pull-ups and risetime accelerators allow for 21 devices. Copyright 2005, PCI-SIG, All Rights Reserved 45

Hot-plug ATNSW# ATNLED AUX PWR Bulk PWR 12V, 3.3V Long Pin Aux Power Host Interface PCI Express Switch PCI Express Hot- Plug Controller RST# Delay PWREN# PRSNT# MPWRGD PERST# Short Pin Short Pin Bulk Power converter Switch Board PCI Express Ref Clock PCI Express Link PCI Express I/O Applications System management Bus Controller System Board WAKE # WAKE # SMBus SMBAlert # System Management Interface Peripheral Board Copyright 2005, PCI-SIG, All Rights Reserved 46

Power Four voltage rails on CompactPCI Express Peripheral Boards Max current defined based on pins Slot Type 12V 3.3V 5V 5Vaux System Slot 30A 15A 15A 1A Peripheral Slot Type 2 2A 3A N/A 1A Copyright 2005, PCI-SIG, All Rights Reserved 47

Power (continued) 12V and 5V must always be greater than 3.3V All rails must be up within 500 milliseconds Ramp up of a rail must be <20 milliseconds Power button is momentary input to System Module Power supply ON/Off controlled by System Module Copyright 2005, PCI-SIG, All Rights Reserved 48

I/O Pin Use and Mechanical Keying ehm connector has keying to deal with I/O pin use: Rear I/O or Not Used (Peripheral Slot) Slot ehm I/O Pin Use Rear I/O or Not Used (System Slot) Extended rear I/O in System Slot PXI Bussed interconnect Board ehm I/O Pin Use Rear I/O OK OK Conflict Conflict Conflict Extended rear I/O on System Board Conflict OK OK Conflict Conflict PXI OK OK Conflict OK Conflict Bussed interconnect OK OK Conflict Conflict OK Not used OK OK Conflict OK OK Copyright 2005, PCI-SIG, All Rights Reserved 50

Summary CompactPCI Express brings PCI Express to the popular CompactPCI form factor that serves many markets CompactPCI Express maintains compatibility with CompactPCI products at the system and slot level CompactPCI Express follows the approach of many existing standards for its electrical requirements Go to www.picmg.org for the CompactPCI Express specification Copyright 2005, PCI-SIG, All Rights Reserved 52