EE 459/5 HL Based igital esign with Programmable Logic Lecture 6 ombinational and sequential circuits Read before class: hapter 2 from textbook Overview ombinational circuits Multiplexer, decoders, encoders, adders, comparators Sequential circuits Regular sequential circuits Finite State Machines
A VHL Template for ombinational Logic entity model_name is port( list of inputs and outputs ); end model_name; architecture arch_name of model_name is begin concurrent statement concurrent statement 2... concurrent statement N; end arch_name; 2-to- Multiplexer LIBRARY ieee; USE ieee.std_logic_64.all; s ENTITY mux2to IS PORT ( w, w, s : IN ST_LOGI; f : OUT ST_LOGI); EN mux2to; ARHITETURE dataflow OF mux2to IS BEGIN f <= w WHEN s = '' ELSE w; EN dataflow ; w w f 2
4-to- Multiplexer LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY mux4to IS PORT ( w, w, w2, w3: IN ST_LOGI; s: IN ST_LOGI_VETOR( OWNTO ); f: OUT ST_LOGI ); EN mux4to ; ARHITETURE dataflow OF mux4to IS BEGIN WITH s SELET f <= w WHEN "", w WHEN "", w2 WHEN "", w3 WHEN OTHERS; EN dataflow s s w w w 2 w 3 f 2-to-4 ecoder LIBRARY ieee; USE ieee.std_logic_64.all; ENTITY dec2to4 IS PORT (w : IN ST_LOGI_VETOR( OWNTO ); En : IN ST_LOGI; y : OUT ST_LOGI_VETOR(3 OWNTO ) ); EN dec2to4 ; ARHITETURE dataflow OF dec2to4 IS SIGNAL Enw : ST_LOGI_VETOR(2 OWNTO ); BEGIN Enw <= En & w ; WITH Enw SELET y <= " WHEN "", "" WHEN "", "" WHEN "", " WHEN "", "" WHEN OTHERS; EN dataflow; En w w y y y 3 2 x x w y 3 w y 2 y En y y 3
4-bit Number omparator: Unsigned LIBRARY ieee ; USE ieee.std_logic_64.all ; USE ieee.std_logic_unsigned.all ; ENTITY compare IS PORT (A, B: IN ST_LOGI_VETOR(3 OWNTO ); AeqB, AgtB, AltB: OUT ST_LOGI ); EN compare; ARHITETURE dataflow OF compare IS BEGIN AeqB <= '' WHEN A = B ELSE ''; AgtB <= '' WHEN A > B ELSE ''; AltB <= '' WHEN A < B ELSE ''; EN dataflow; 4 4 A B AeqB AgtB AltB 4-bit Number omparator: Signed LIBRARY ieee; USE ieee.std_logic_64.all; USE ieee.std_logic_signed.all; ENTITY compare IS PORT (A, B: IN ST_LOGI_VETOR(3 OWNTO ); AeqB, AgtB, AltB: OUT ST_LOGI ); EN compare; ARHITETURE dataflow OF compare IS BEGIN AeqB <= '' WHEN A = B ELSE ''; AgtB <= '' WHEN A > B ELSE ''; AltB <= '' WHEN A < B ELSE ''; EN dataflow; 4
Tri-state Buffer x e x e f Z Z f ENTITY tri_state IS PORT ( e: IN ST_LOGI; x: IN ST_LOGI; f: OUT ST_LOGI); EN tri_state; ARHITETURE dataflow OF tri_state IS BEGIN f <= x WHEN (e = ) ELSE Z ; EN dataflow; Priority Encoder w w w 2 w 3 y y z LIBRARY ieee ; USE ieee.std_logic_64.all ; ENTITY priority IS PORT ( w: IN ST_LOGI_VETOR(3 OWNTO ) ; y: OUT ST_LOGI_VETOR( OWNTO ) ; z: OUT ST_LOGI ) ; EN priority ; w 3 w 2 x w x x w y x x x d y d z ARHITETURE dataflow OF priority IS BEGIN y <= "" WHEN w(3) = '' ELSE "" WHEN w(2) = '' ELSE "" WHEN w() = '' ELSE "" ; z <= '' WHEN w = "" ELSE '' ; EN dataflow ; 5
Most often implied structure When - Else target_signal <= value when condition else value2 when condition2 else... valuen- when conditionn- else valuen; Value N Value N- ondition N- Value 2 Value Target Signal ondition 2 ondition Most often implied structure With - Select - When with choice_expression select target_signal <= expression when choices_, expression2 when choices_2,... expressionn when choices_n; expression expression2 choices_ choices_2 target_signal expressionn choices_n choice expression 6
Overview ombinational circuits Multiplexer, decoders, encoders, adders, comparators Sequential circuits Regular sequential circuits Finite State Machines Sequential ircuits Regular sequential circuits Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Finite State Machines (FSMs) State tables & state diagrams 7
Sequential circuits general description A Sequential circuit contains: Storage elements: Latches or Flip-Flops ombinational Logic: implements a multiple-output switching function Next state function: Next State = f(inputs, State) Output function: two types Mealy: Outputs = g(inputs, State) Moore: Outputs = h(state) Inputs State ombinational Logic Storage Elements Outputs Next state Latches R (reset) S (set) S (set) Basic S-R latch R (reset) Basic S-R latch S R locked S-R latch latch 8
Edge-Triggered Flip-Flop The change of is associated with the negative edge at the end of the pulse - negative-edge triggered flip-flop. S R lock Triggered Modelling of Flip-Flops Library IEEE; use IEEE.Std_Logic_64.all; entity FLOP is port (, LK : in std_logic; : out std_logic); end FLOP; architecture A of FLOP is begin process begin wait until LK event and LK= ; <= ; end process; end A; 9
irect Inputs At power-up or at reset, sequential circuit usually is initialized to a known state before it begins operation one outside of the clocked behavior of the circuit (i.e., asynchronously). irect R/S inputs For the example flip-flop shown applied to R resets the flip-flop to the state applied to S sets the flip-flop to the state S R Positive Edge-triggered Flip-flop with Asynchronous Set/Reset library IEEE; use IEEE.std_logic_64.all; entity ASYN_FF is port (, LK, SETN, RSTN : in std_logic; : out std_logic); end ASYN_FF; architecture RTL of ASYN_FF is begin process (LK, RSTN, SETN) begin if (RSTN = ``) then <= ``; elsif SETN ='' then <= ''; elsif (LK event and LK = ) then <= ; end if; end process; end RTL;
Registers Register: the simplest storage component in a computer, a bit-wise extension of a flip-flop. Registers can be classified into Simple Registers Parallel-Load Registers Shift Registers Simple Registers I 3 I 2 I I 3 3 2 2 clk 3 2 lk I 3 I 2 I I 3 2 A simple register consists of N flip-flops driven by a common clock signal. Has N inputs and N outputs in addition to the clock signal.
Register with asynchronous preset and clear Preset clk clear I 3 I 2 I I 3 2 Preset I 3 I 2 I I 3 3 2 2 clk lear 3 2 Library ieee; USE ieee.std_logic_64.all; ENTITY simple_register IS GENERI ( N : INTEGER := 4); PORT ( I : IN ST_LOGI_VETOR (N- OWNTO ); lock, lear, Preset : IN ST_LOGI; : OUT ST_LOGI_VETOR (N- OWNTO )); EN simple_register; ARHITETURE simple_memory OF simple_register IS BEGIN PROESS (Preset, lear, lock) BEGIN IF Preset = ' THEN <= (OTHERS => ');; ELSIF lear = '' THEN <= (OTHERS => ''); ELSIF (lock'event AN lock = '') THEN <= I; EN IF; EN PROESS; EN simple_memory; 2
Parallel Load Registers In the previous registers, new data is stored automatically on every rising edge of the clock. In most digital systems, the data is stored for several clock cycles before it is rewritten. For this reason it is useful to be able to control WHEN the data will be entered into a register. Use a control signal called Load or Enable. This allows loading into a register known as a parallelload register. Library ieee; USE ieee.std_logic_64.all; ENTITY load_enable IS GENERI ( N : INTEGER := 4); PORT ( : IN ST_LOGI_VETOR (N- OWNTO ); lock, Resetn, load : IN ST_LOGI; : BUFFER ST_LOGI_VETOR (N- OWNTO )); EN load_enable; ARHITETURE rtl OF load_enable IS SIGNAL state : std_logic_vector(n- OWNTO ); BEGIN PROESS (Resetn, lock) IS BEGIN IF Resetn = '' THEN state <= (OTHERS => ''); ELSIF (lock'event AN lock = '') THEN IF load = '' THEN state <= ; ELSE state <= state; EN IF; EN IF; EN PROESS; <= state; EN rtl; 3
Timing diagram for parallel-load register Serial-in/Parallel-out Shift Register 4
Parallel Load Shift Register Library ieee; USE ieee.std_logic_64.all; VHL for Up-ounter USE ieee.std_logic_unsigned.all; ENTITY upcount IS GENERI ( N : INTEGER := 4 ); PORT ( lock, Resetn, Enable : IN ST_LOGI; : BUFFER ST_LOGI_VETOR (N- OWNTO )); EN upcount; ARHITETURE cnt OF upcount IS SIGNAL count : ST_LOGI_VETOR (N- OWNTO ); BEGIN PROESS (Resetn, lock) BEGIN IF Resetn = '' THEN count <= ( OTHERS => ); -- Use of others in aggregate makes your code generic. -- Thus you won't have to replace all "" with -- "" when you change your mind and vectors should -- be only 2 bits wide. ELSIF (lock'event AN lock = '') THEN IF Enable = '' THEN count <= count +; ELSE count <= count; EN IF; EN IF; EN PROESS; <= count; EN cnt; 5
Timing iagram for Up-ounter Synchronous ounters Internal logic Incrementer: + or + ontraction of a ripple carry adder with one operant fixed at X Symbol for synchronous counter: TR 4 Incrementer 2 EN 2 3 3 O Symbol 6
Synchronous ounters (ontd.) ontraction of carry-lookahead adder Reduce path delays alled parallel gating Lookahead can be used on Os and ENs to prevent long paths in large counters EN 2 2 3 3 O Logic iagram-parallel Gating ounter with Parallel Load Load ount Action Load Hold Stored Value ount Up Stored Value X Load ount Add path for input data enabled for Load = Add logic to: When Load = disable count logic (feedback from outputs) When Load = and ount = enable count logic 2 2 TR4 Load ount 2 3 2 3 O lock 3 arry Output O 3 7
B ounter architecture Behavioral of bcd_counter is signal regcnt : std_logic_vector(3 downto ); begin count: process (reset, clk) is begin if ( reset='' ) then regcnt <= ""; elsif ( clk'event and clk='') then regcnt <= regcnt+; if (regcnt = "") then regcnt <= ""; end if; end if; end process; end Behavioral; Overview ombinational circuits Multiplexer, decoders, encoders, adders, comparators Sequential circuits Regular sequential circuits Finite State Machines (FSMs) 8
FSM types MEALY machine: Outputs are dependent on current state and inputs MOORE machine: Outputs are dependent on current state only Inputs Outputs Inputs Logic Logic State Next State State Next State Memory Outputs Logic Memory Example Input: x(t) Output: State: y(t) (A(t), B(t)) x Next State A A Output Function? y(t) = x(t)(b(t) + A(t)) Next State Function? A(t+) = A(t)x(t) + B(t)x(t) B(t+) = A(t)x(t) P Output ' B y 9
Example (ontd.) Where in time are inputs, outputs and states defined? y(t) = x(t)(b(t) + A(t)) A(t+) = A(t)x(t) + B(t)x(t) B(t+) = A(t)x(t) Typical esign Procedure for Sequential ircuits Formulation: onstruct a state table or state diagram State Assignment: Assign binary codes to the states Flip-Flop Input Equation etermination: Select flip-flop types, derive flip-flop input equations from next state entries in the table Output Equation etermination: erive output equations from output entries in the table Optimization - Optimize the equations Technology Mapping - Find circuit from equations and map to flip-flops and gate technology Verification - Verify correctness of final design 2
Example 2: Sequence Recognizer A sequence recognizer: produces an output whenever a prescribed pattern of inputs occur in sequence Steps: Begin in an initial state (typically reset state), when NONE of the initial portion of the sequence has occurred Add states That recognize each successive symbol occurring The final state represents the input sequence occurrence Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred Add other arcs on non-sequence inputs which transition to states The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since reset Example 2: Recognize as Mealy machine efine states for the sequence to be recognized Starting in the initial state ("A"): / / / / A B Finally, output on the arc from means the sequence has been recognized, To what state should the arc from state go? Remember:? The final in the recognized sequence is a sub-sequence of. It follows a which is not a sub-sequence of. Thus it should represent the same state reached from the initial state after a first is observed. A / / / B / 2
Example 2: Recognize (ontd.) The other arcs are added to each state for inputs not yet listed. Which arcs are missing? State transition arcs must represent the fact that an input subsequence has occurred. Note that the arc from state back to implies that State means two or more 's have occurred. / / A / / B / / / / Present Next State State x= x= Output x= x= A A B B A A B Example 2: Recognize as Moore machine For Moore Model, outputs are associated with states. Arcs now show only state transitions Add a new state E to produce the output State E produces the same behavior in the future as state B, but it gives a different output at the present time. Thus these states do represent a different abstraction of the input history. The Moore model for a sequence recognizer usually has more states than the Mealy model. / / A / B / / / / / A/ B/ / / E/ 22
Example 2: Moore Model (ontd.) A/ B/ / / E/ Present State Next State x= x= A A B B A A E E A Output y VHL code using 3 processes: sequential recognizer library ieee; use ieee.std_logic_64.all; entity seq_rec_mealy is port (LK, RESET, X: in std_logic; Z: out std_logic); end seq_rec; architecture process_3 of seq_rec_mealy is type state_type is (A, B,, ); signal state, next_state: state_type; / / begin A / B / / / / / 23
-- process : implements positive edge-triggered -- flipflop with asynchronous reset state_register: process (LK, RESET) begin if (RESET = '') then state <= A; elsif (LK'event and LK = '') then state <= next_state; end if; end process; -- process 2: implement output as function -- of input X and state output_function: process (X, state) begin case state is when A => Z <= ''; when B => Z <= ''; when => Z <= ''; when => if X = '' then Z <= '; A else Z <= '; end if; end case; end process; / / / B / / / / / -- process 3: next state-function implemented -- as a function of input X and state next_state_function: process (X, state) begin case state is when A => if X = '' then next_state <= B; else next_state <= A; end if; when B => if X = '' then next_state <= ; else next_state <= A; end if; when => if X = '' then next_state <= ; else next_state <= ; end if; when => / if X = '' then next_state <= B; else next_state <= A; / end if; A end case; end process; / end architecture; B / / / / / 24
Summary ombinational circuits and regular sequential circuits are somewhat easier to describe in VHL. Manual design of Finite State Machines becomes difficult for complex circuits. Automated tools come in handy in this case. Appendix A: VHL elay Models elay is created by scheduling a signal assignment for a future time elay in a VHL cycle can be of several types: Inertial Transport elta 25
Inertial elay efault delay type Allows for user specified delay Absorbs pulses of shorter duration than the specified delay Transport elay Must be explicitly specified by user Allows for user specified delay Passes all input transitions with delay 26
elta elay elta delay needed to provide support for concurrent operations with zero delay The order of execution for components with zero delay is not clear Scheduling of zero delay devices requires the delta delay A delta delay is necessary if no other delay is specified A delta delay does not advance simulator time or real/wall clock time One delta delay is an infinitesimal amount of time The delta is a scheduling device to ensure repeatability (or determinism) Example elta elay 27