SoC Memory Interfaces. Today and tomorrow at TSMC 2013 TSMC, Ltd

SoC Memory Interfaces. Today and tomorrow at TSMC 2013 TSMC, Ltd

2 Agenda TSMC IP Ecosystem DDR Interfaces for SoCs Summary

3 TSMC Highlights Founded in 1987 The world's first dedicated semiconductor foundry Fabs in Taiwan, U.S.A., Singapore and China 2012 total managed capacity reached 15.1 million 8 wafer equivalents 2012 total revenue reached a new high at US$17.12 billion

4 ASIC to Fabless Full custom/idm only Era TSMC Founded 1987 ASIC Era Fabless Era Manufacturing Complexity Designer semiconductor expertise & bandwidth Gap 10 µm 3 µm + LDE 1.5 µm 1 µm 0.8 µm 0.35 µm 180 130 65 1970 1980 1990 2000

ICC Incubatio n Centers of China ICC Incubation Centers of China 5 Fabless to OIP Manufacturing Complexity Full custom/idm only Era TSMC Founded 1987 ASIC Era OIP Fabless Era Manufacturing Complexity OIP Era Gap Designer semiconductor Designer expertise & semiconductor bandwidth expertise & bandwidth Gap 10 µm 3 µm + LDE 1.5 µm 1 µm 0.8 µm 0.35 µm 180 130 65 40 28 20 16 1970 1980 1990 2000 2010

6 OIP Era Characteristics Semiconductor shipments booming Huge opportunities driven by convergence devices and emerging markets Cadence Founded 1988 Semiconductor suppliers need incredible TSMC Founded 1987 Foundry amounts of EDA and IP support Era Full custom/idm ASIC Era Customers continue to invest in R&D, but only Era with increasingly intense focus on design OIP Era Manufacturing Complexity Gap Designer semiconductor expertise & bandwidth Gap Customers 10 3 look 1.5 to Foundry 1 0.8 and 0.35 EDA/IP 180 130 µm µm µm µm µm µm for more and more design support 1970 1980 1990 2000 2010 65 40 28 20 16

7 OIP Era Challenge Manpower for Leading Edge Designs (Normalized to N65) 8 7 6 Complexity 5 4 3 IP Qualification & Sourcing Physical Design & Verification Architecture Design System Verification 2 1 0 Source: I.B.S. N65 N40 N28 N20 16FF OIP Era

8 OIP Era Challenge = EDA + IP Manpower for Leading Edge Designs (Normalized to N65) 8 7 Physical 6 Design and Verification impacted by IP sourcing 5 IP Sourcing from multiple vendors Verifying individual IP Cross-verifying multiple IP IP Qualification & Sourcing Physical Design & Verification Architecture Design System Verification 4 3 2 OIP Era

9 OIP Era Opportunity = EDA + IP Manpower for Leading Edge Designs (Normalized to N65) 8 7 6 5 OIP TSMC 9000 IP Qualification & Sourcing Physical Design & Verification Architecture Design System Verification 4 3 2 OIP Era

10 OIP Objective: Reduced Effort Decrease IP Sourcing Effort Increase IP Quality Increase IP Integration with Tools ALL in Synchronization with TSMC Process Development 8 Goal 7 6 5 OIP TSMC 9000 IP Qualification & Sourcing Physical Design & Verification 4 3 2 1 0 OIP Era

11 OIP Ecosystem Summary

Comprehensive IP Portfolio 5,400+ IP titles from over 40+ IP vendors MIPI SATA MTP/OTP CPU Core SD/MMC PCIe/PCIx ADC/DAC Electrical Fuse SRAM DDR Oscilator Embedded DRAM PLL LVDS USB Voltage Regulator Embedded Flash Standard Cell / IO XAUI IIC/IIS Analog IP Embedded Memory Foundation IP Embedded CPU Interface IP 2013 TSMC, Ltd

13 Contribution from OIP Partners IP

14 Agenda TSMC IP Ecosystem DDR Interfaces for SoCs Summary

15 DDR Interfaces today in TSMC Server DDR3 and DDR4 PHYs Mobile LPDDR2, LPDDR3 Legacy DDR, DDR2

16 DDR Interfaces. Near future IP available and under development for all popular process nodes Detailed information available

17 DDR Interfaces. Near future

18 TSMC s Crystal ball Increase bandwidth while lowering power and conflicting goals Parallel interfaces are running out of steam LPDDR4, 3.2Gbps. Is it still low power memory? The days of a dominant memory interface anchored by the PC are over i.e. DDR DIMMs DDR PHY market is segmenting along major semiconductor segments Mobile, Server, Networking

19 Different needs, different solutions Power HMC DDR3 DDR4 HBM DDR3U, DDR3L LPDDR2 LPDDR3 LPDDR4 Wide IO2 Bandwidth

20 Different needs, different solutions HMC Price HBM Wide IO2 LPDDR2 LPDDR3 LPDDR4 DDR3U, DDR3L DDR3 DDR4 Bandwidth

21 Cutting the knot The parallel DDR roadmap is getting to its end The solution is new signaling New signaling will require new physical support TSV (through silicon vias) in 2.5D and 3D configurations are expected to be solution of choice after LPDDR4 TSMC s TSV solution is called CoWoS TM Substrate chip 20mm chip chip CoWoS TM chip chip chip 0.03mm PCB

22 CoWoS TM in Production FPGA FPGA FPGA FPGA DRAM SoCDRAM SoC DRAM WideIO DRAM In production Demonstrated Enabled FPGA system integration for networking applications to gain 2.5D IC technology leadership in 28 and beyond Delivered CoWoS TM product units and achieved >95% inhouse production yield Deployed CoWoS TM Design Reference Flow

23 CoWoS TM Technology Direction Develop CoWoS TM module with more top dies Integrate high bandwidth memory Mobile, Server: Wide IO2 GPU, Networking: HBM HBM requires interposer, which is part of CoWoS

24 Agenda TSMC IP Ecosystem DDR Interfaces for SoCs Summary

25 Summary TSMC partners provide DDR PHY interfaces for SoC designs in all main logic processes The DDR PHY market will segment following the DRAM market TSMC and its partners are working today to provide the solutions that SoCs will need tomorrow DDR4 LPDDR4 TSV technology: Wide IO2 SerDes technology: HBM, HCM

26 TSMC 2013 TECHNOLOGY SYMPOSIUM 2013 2011 TSMC, TSMC, Ltd Ltd