Synopsys Design Platform
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1 Synopsys Design Platform Silicon Proven for FDSOI Swami Venkat, Senior Director, Marketing, Design Group September 26, Synopsys, Inc. 1
2 Synopsys: Silicon to Software Software Application security testing & quality Leader in Gartner s Magic Quadrant Verification Fastest engines & unified platform HW/SW verification & early SW bring-up IP Broadest portfolio of silicon-proven IP #1 interface, analog, embedded mem. & phys. IP Design Digital & custom AMS platforms Best quality of results & highest productivity Silicon TCAD, lithography tools & yield optimization Down to 5nm & below 2017 Synopsys, Inc. 2
3 PrimeTime HSPICE, CustomSim Trusted Anchors, Correlated Platform SYNOPSYS DESIGN PLATFORM Design Compiler Custom Compiler Best, Trusted Anchor Products #1 Synthesis, #1 P&R, #1 Signoff Shared Optimization Technology Full support for FD-SOI biasing Design IC Compiler II Layout IC Validator, StarRC Correlated Platform with Value Links PrimeTime and StarRC inside ICC II Reduced pessimism with Advanced GBA In-Design Physical Signoff Co-Design Custom Implementation 2016 Synopsys, Inc. 3
4 Process Type for Current Designs 50% 45% 40% 35% 30% 25% 20% 15% 10% 5% 0% 46% Planar MOSFET (CMOS) 34% FinFET 9% Partial/Fully Depleted-SOI 5% FPGA Source: 2016 Global User Survey N = 2,071 7% Other 2017 Synopsys, Inc. 4
5 Innovation through Collaboration Continues News Release: September 20, 2017 News Release: September 25, 2017 Synopsys Design Platform Certified by GLOBALFOUNDRIES for 22nm FD-SOI (22FDX ) Process Technology Certification Enables Optimized Implementation and Predictable Signoff Highlights: Certified IC Compiler II, IC Validator, PrimeTime, and StarRC tools for implementation and signoff of 22FDX designs Based on silicon-proven RTL-to-GDS 22FDX Foundry Reference Flow, utilizing automated UPF-driven bias voltage support Certified with Synopsys high-performance DesignWare Embedded Vision (EV) Processor IP; applies real-world requirements for optimal performance, power and area A reference flow with certified tools enables our mutual customers to take advantage of FinFET-like performance and energy efficiency at a cost comparable to 28-nm planar technologies. Jai Durgam VP, Customer Design Enablement GLOBALFOUNDRIES Samsung Certifies Synopsys Design Platform for 28nm FD-SOI Process Technology Reference Flow and IP for Silicon-Proven Design Platform Accelerates Path to Lower Power & Design Cost Highlights: 28FDS process is ideal for IoT, mobile and automotive applications Comprehensive certification includes digital, custom and SPICE tools of the Synopsys Design Platform Availability of certified Synopsys Design Platform, PDK and reference flow will allow our mutual customers to accelerate adoption of our 28FDS technology. Jaehong Park Sr. VP, Foundry Solutions Team Samsung Electronics 2017 Synopsys, Inc. 5
6 FD-SOI Innovation through Collaboration 2017 Synopsys, Inc. 6
7 Recent Design Platform FD-SOI Success 2017 Synopsys, Inc. 7
8 Long History of Design Platform Success for FD-SOI 2017 Synopsys, Inc. 8
9 2017 Synopsys, Inc. 9
10 Synopsys Design Platform is FDSOI-Ready Certified & enabled for 28nm & 22nm FD-SOI process technologies Function (Tools) FinFET Readiness Technology Modeling (Sentaurus) Extraction (StarRC) Modeling (HSPICE) Place & Route (IC Compiler II) Physical Verification (IC Validator) Signoff (PrimeTime) Custom Design (Custom Designer) Characterization (SiliconSmart) 2016 Synopsys, Inc. 10 Synopsys Confidential
11 VDD PD1 NW PD2 Synopsys Design Platform Supports FD-SOI Biasing Typical usage scenarios Dynamic tuning of performance/leakage in normal operation Use forward or reverse biasing to adjust the performance or leakage VSS PW Front-End Further reduction of leakage in standby mode Use reverse biasing to put the device into a standby mode offering faster wake-up time vs. shutdown mode VDD Rail VSS Rail NW Rail Back-End PW Tap Tap Cell Two implementation methodologies fully supported 1. Classic: Bias rails inserted and connected during P&R Post-route Verilog netlist has bias pins which can be verified 2. Power intent-based full flow Specification via Unified Power Format (UPF) using supply sets Supported throughout implementation and verification flow Comprehensive checks: rail order, connectivity & other (error if negative voltages are specified on NWELL supply nets) 2017 Synopsys, Inc. 11
12 UPF-Based FD-SOI Bias Support DC: Synthesis with bias connectivity on power domains VCS NLP, VC LP: Verification of connectivity and functionality IC Compiler II: Tap cell array determines power routes required and writes out Verilog netlist with bias rails IC Validator: LVS and In-Design automatic DRC of bias rails StarRC: Bias-rail aware extraction Formality: Equivalence checking using netlist with bias rails PrimeTime PX: Bias rail gate-level analysis PrimeTime: Bias-aware signoff with scaling of bias libs 2017 Synopsys, Inc. 12
13 PrimeTime Supports Scaling for Bias Accurate scaling methodology is available today for bias libraries PrimeTime Voltage Scaling 0.86v 1.12v Smart scaling technology achieves signoff accurate delay and variation scaling 5 libraries enable scaling over the entire operating range for most designs Device Speed 0.45v 0.54v 0.68v 0.49v (Scaled) 0.49V Uncoupled Path (Scaling Results) Signoff Accurate Low Voltage Scaling 2017 Synopsys, Inc. 13
14 Accuracy Correlation for Scaled Voltages Corner VNW/VPW Passing Rate (%) SS_0.72_M40C 0.0/ SS_0.72_M40C 0.5/ FF_0.88_125C 0.0/ FF_0.88_125C 0.5/ TT_0.8_25C 0.5/ TT_0.8_25C 0.5/ TT_0.8_25C 0.5/ TT_0.8_25C 0.25/ SPICE accuracy correlates with average passing rate of 99.3% 2017 Synopsys, Inc. 14
15 Sentaurus TCAD Analyzes Critical Characteristics Of FDSOI Devices Supports Research and Development Phases Proven Track Record for SOI Modeling 2016 Synopsys, Inc. 15
16 DesignWare 28-nm FD-SOI IP Portfolio With Interoperable Digital Controllers Analog IP Interface IP ADC 10-bit, up to 2MSPS ADC 12-bit up to 5 MSPS Audio Codec 24-bit Video DAC 10-bit up to 300 MSPS USB 2.0 PHY USB 3.0 PHY PCIe 2.1 PHY PCIe 3.0 PHY DDR3/2 PHY LPDDR4 PHY XAUI PHY SATA PHY MIPI D-PHY MIPI M-PHY 2017 Synopsys, Inc. 16
17 Custom Compiler is Ready for FD-SOI Custom Compiler deployed for production 28nm FD-SOI use at STMicroelectronics Custom Compiler ipdks available for 28nm and 22nm FD-SOI technologies from merchant foundries Custom Compiler s unique visually-assisted automation reduced FD-SOI memory IP layout time by 25%* *Source: Improving Memory Compiler Development Efficiency Using Custom Compiler, Sachin Gulyani, STMicroelectronics, SV SNUG March Synopsys, Inc. 17
18 Comprehensive Circuit Simulation Solution Ready for 28/14nm FD-SOI at IDM and foundries HSPICE, FineSim SPICE, CustomSim Support latest UTSOI device models Support device aging simulation HSPICE Used for device model parameter extraction and analog block simulation FineSim SPICE Accelerates simulation of complex post-layout analog circuits CustomSim Primary FastSPICE for all applications, Simulator for internal SRAM compiler Mixed-signal verification of SoC Low power and ERC checking with Circuit Check Advanced device model support Models Versions BSIM , PSP 103.2, BSIMSOI , 4.4, 4.5 BSIM-CMG , , 106.1, 107.0, UTSOI 1.14f, 2.00g, 2.2 BSIM6 6.0; HiSim HV 1.24, 2.1, Hicum 1.31, 2.32, Maxtram , Synopsys, Inc. 18
19 What s Next? Synopsys Ready for 14nm FD-SOI Design Compiler Graphical, IC Compiler, PrimeTime & StarRC Tapeout Success 2016 Synopsys, Inc. 19 Source: Synopsys Research, 2014 (14 Nanometer FD-SOI, 2.3M Instances)
20 Summary FD-SOI does represent a revolutionary evolution in semiconductor technology Better performance/power envelope vs. bulk CMOS Lower cost vs. FinFET Multi-year collaboration with industry leaders has yielded excellent results in helping designers achieve the best QoR with FD-SOI Minimal impact to existing design flows Synopsys Design Platform is ready and silicon-proven across multiple FD-SOI process technologies Lowers design and silicon cost Handles very large, complex designs Provides optimal performance, power and area benefits 2017 Synopsys, Inc. 20
21 Thank You
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