Overview of Digital Design Methodologies

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Transcription:

Overview of Digital Design Methodologies ELEC 5402 Pavan Gunupudi Dept. of Electronics, Carleton University January 5, 2012 1 / 13

Introduction 2 / 13

Introduction Driving Areas: Smart phones, mobile devices, computers, communication Increased complexity, miniaturization, increased operating frequencies Moores Law: Exponential - Technology and EDA Tools EDA Tools are an integral part of the design cycle 3 / 13

CAD/EDA Tools Once upon a time.. microprocessors were manually designed How do you design a circuit with 2 billion transistors??!! CAD tools aided in semiconductor electronics development Different names: CAD, CAQ, CAP, CAS, CAM (CAX for short). EDA Tools achieve automation using CAX tools. 4 / 13

Digital Design Abstractions BEHAVIORAL DOMAIN Systems Algorithms Register transfers Logic Transfer functions STRUCTURAL DOMAIN Processors ALU s, RAM, etc. Gates, flip-flops, etc. Transistors Transistor layout Cell layout Module layout Floorplans Physical partitions PHYSICAL DOMAIN 5 / 13

Advantage of Abstraction B E F G H I A M C K J L D N O A Level 1 B C D Level 2 J Level 3 E F G H I M N O Level 4 K L (a) (b) A B D C I C J E G F H A I M N K L O (c) (d) (e) 6 / 13

Design Flow BEHAVIORAL DOMAIN STRUCTURAL DOMAIN Systems Algorithms Register transfers Logic Transfer functions Processors ALU s, RAM, etc. Gates, flip-flops, etc. Transistors Transistor layout Cell layout Module layout Floorplans Physical partitions PHYSICAL DOMAIN 7 / 13

Top Down Design Start with an idea Creation of specifications Create behavioural models (Verilog/VHDL - RTL Desc.) Convert the RTL description to gate level netlist (synthesis) Iterate between RTL and gate level using simulation Convert gate-level netlist to a layout Perform place and route Iterate between layout level and RTL level Design ready to go to fabrication 8 / 13

First generation EDA Tools Early layout was manual; polygons were cutout for mask making Berkeley Spice introduced in 1975 laid foundation for EDA tools Polygon data for layouts was entered into computers/design rule checks still a burden of the user Geometric checks (DRC: Design Rule Check) were introduced Layout extraction (layout versus schematic check) The jump from Boolean equations to Gates/Flip-flops was manual The jump from Gates/Flip-flops to polygons was also manual Only verification was automated 9 / 13

Second Generation Started around 80s Automatic place and route was introduced Logic simulators came into being - Circuits have only three states (0,1,X=unknown) The jump from behavioural to structural to attain a gate level netlist was manual All other lower level work was automated 10 / 13

Third Generation Automation work started in universities silicon compiler Automate all the way to Silicon was not so practical HDL languages such as VHDL (1987) and Verilog were introduced Synopsis introduced DesignCompiler (logic synthesis) and HDL compiler (RTL synthesis) Acceptance for these tools was slow early on: Heavy price tag Think different: think RTL not schematic Quality was not as good as manual designs Universities taught HDL languages in 90s leading to later acceptance 11 / 13

Third Generation Verification Automatic test pattern generation Large number of input datasets needed ((2ˆn) inputs + memory) Synthesize such that circuit is testable Static timing analysis Calculates the gate delays along signal path to verify timing The maximum and minimum delays are considered for further analysis Formal verification Verify by constructing original function from synthesized circuit 12 / 13

Fourth Generation Outlook Design Reuse Synthesis of RF/analog circuits Algorithmic to RTL description Signal Integrity Multidisciplinary simulation electrical, optical thermal Emerging: Bio-Design-Automation; synthetic biology Journal: IEEE Transactions on Computer-Aided Design of ICs 13 / 13

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