In Class Assignment 2

Similar documents
Tasks. Task Implementation and management

Exam TI2720-C/TI2725-C Embedded Software

What s An OS? Cyclic Executive. Interrupts. Advantages Simple implementation Low overhead Very predictable

Introduction to Real-Time Operating Systems

Preview. Process Scheduler. Process Scheduling Algorithms for Batch System. Process Scheduling Algorithms for Interactive System

Deadlock. Concurrency: Deadlock and Starvation. Reusable Resources

Real-Time Programming

Chapter 5: CPU Scheduling

General Objectives: To understand the process management in operating system. Specific Objectives: At the end of the unit you should be able to:

OS 1 st Exam Name Solution St # (Q1) (19 points) True/False. Circle the appropriate choice (there are no trick questions).

Lecture notes Lectures 1 through 5 (up through lecture 5 slide 63) Book Chapters 1-4

RT3 - FreeRTOS Real Time Programming

CSC Operating Systems Spring Lecture - XII Midterm Review. Tevfik Ko!ar. Louisiana State University. March 4 th, 2008.

CS 571 Operating Systems. Midterm Review. Angelos Stavrou, George Mason University

Part B Questions. Unit I

AVR XMEGA Product Line Introduction AVR XMEGA TM. Product Introduction.

COSC243 Part 2: Operating Systems

The components in the middle are core and the components on the outside are optional.

CS 326: Operating Systems. CPU Scheduling. Lecture 6

EMBEDDED SYSTEMS PART A UNIT-1

Review. Preview. Three Level Scheduler. Scheduler. Process behavior. Effective CPU Scheduler is essential. Process Scheduling

Interrupts and Time. Real-Time Systems, Lecture 5. Martina Maggio 28 January Lund University, Department of Automatic Control

Chapter 6 PROGRAMMING THE TIMERS

COMP 300E Operating Systems Fall Semester 2011 Midterm Examination SAMPLE. Name: Student ID:

Zilog Real-Time Kernel

Mobile Operating Systems Lesson 01 Operating System

1.1 CPU I/O Burst Cycle

Interrupts and Time. Interrupts. Content. Real-Time Systems, Lecture 5. External Communication. Interrupts. Interrupts

Interrupts. Embedded Systems Interfacing. 08 September 2011

Operating Systems Comprehensive Exam. Spring Student ID # 2/17/2011

Concurrency: Deadlock and Starvation

MCS-51 Serial Port A T 8 9 C 5 2 1

Interrupts Peter Rounce - room 6.18

Micrium µc/os II RTOS Introduction EE J. E. Lumpp

Lecture 9: Midterm Review

Lab 2 - RASPNet layer 1 und 2

CS-537: Midterm Exam (Spring 2001)

Operating Systems Comprehensive Exam. Spring Student ID # 3/16/2006

Embedded System Curriculum

Programming Embedded Systems

EE458 - Embedded Systems Lecture 8 Semaphores

EECS 373 Midterm 2 Fall 2018

Interrupt/Timer/DMA 1

Lecture Topics. Announcements. Today: Uniprocessor Scheduling (Stallings, chapter ) Next: Advanced Scheduling (Stallings, chapter

Class average is Undergraduates are performing better. Working with low-level microcontroller timers

Timers 1 / 46. Jiffies. Potent and Evil Magic

EE 472 Embedded Systems. Name solutions. Instructions:

M68HC08 Microcontroller The MC68HC908GP32. General Description. MCU Block Diagram CPU08 1

CSE 153 Design of Operating Systems

GLOSSARY. VisualDSP++ Kernel (VDK) User s Guide B-1

CMPS 111 Spring 2013 Prof. Scott A. Brandt Midterm Examination May 6, Name: ID:

Midterm Exam. October 20th, Thursday NSC

UNIT:2. Process Management

HC12 Built-In Hardware

Frequently asked questions from the previous class survey

Techno India Batanagar Department of Computer Science & Engineering. Model Questions. Multiple Choice Questions:

Arduino Uno R3 INTRODUCTION

Computer Systems Assignment 4: Scheduling and I/O

Interrupts Peter Rounce

ARDUINO MEGA INTRODUCTION

Main Points of the Computer Organization and System Software Module

Operating Systems Comprehensive Exam. Spring Student ID # 3/20/2013

Operating System Concepts Ch. 5: Scheduling

University of Washington EE 472: Microcomputer Systems Exam Autumn 2015

TEVATRON TECHNOLOGIES PVT. LTD Embedded! Robotics! IoT! VLSI Design! Projects! Technical Consultancy! Education! STEM! Software!

Final Exam Study Guide

CS140 Operating Systems and Systems Programming Midterm Exam

TDDB68 Processprogrammering och operativsystem / Concurrent programming and operating systems

CS153: Midterm (Winter 19)

(b) External fragmentation can happen in a virtual memory paging system.

Lecture 14. Ali Karimpour Associate Professor Ferdowsi University of Mashhad

CSE 120 Principles of Computer Operating Systems Fall Quarter, 2001 Midterm Exam. Instructor: Geoffrey M. Voelker

CSE 120 PRACTICE FINAL EXAM, WINTER 2013

SYNCHRONIZATION M O D E R N O P E R A T I N G S Y S T E M S R E A D 2. 3 E X C E P T A N D S P R I N G 2018

Chapter 2. Overview of Architecture and Microcontroller-Resources

Designing Responsive and Real-Time Systems

Concurrency. Chapter 5

CPU Scheduling. CSE 2431: Introduction to Operating Systems Reading: Chapter 6, [OSC] (except Sections )

Scheduling (Win 2K) CSE Computer Systems November 21, 2001

MICROPROCESSOR BASED SYSTEM DESIGN

Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology

Bare Metal Application Design, Interrupts & Timers

Faculty of Electrical Engineering, Mathematics, and Computer Science Delft University of Technology

Embedded Operating Systems

Course Syllabus. Operating Systems

16-BIT TIMER AND EVENT COUNTER

1. Background. 2. Demand Paging

Uniprocessor Scheduling

AVR XMEGA TM. A New Reference for 8/16-bit Microcontrollers. Ingar Fredriksen AVR Product Marketing Director

CSE120 Principles of Operating Systems. Prof Yuanyuan (YY) Zhou Scheduling

Lecture 5 / Chapter 6 (CPU Scheduling) Basic Concepts. Scheduling Criteria Scheduling Algorithms

Multiprocessor and Real-Time Scheduling. Chapter 10

CS370 Operating Systems

CPU Scheduling. Daniel Mosse. (Most slides are from Sherif Khattab and Silberschatz, Galvin and Gagne 2013)

Processor and compiler dependent

Operating Systems. Designed and Presented by Dr. Ayman Elshenawy Elsefy

Process- Concept &Process Scheduling OPERATING SYSTEMS

Ch 4 : CPU scheduling

Operating Systems Comprehensive Exam. Fall Student ID # 10/31/2013

Intertask Communication

Transcription:

In Class Assignment 2 Name: UMBC ID: Academic Integrity Statement: "Integrity of scholarship is essential for an academic community. The University expects that students will honor this. By signing this, you state that all work for this exam is performed by the individual to whom it is assigned, without unauthorized aid of any kind." Signature: Directions: Each section will have one theoretical question and one application question over a topic covered in class. Each question will be worth 10% of the total points allocated for the assignment. Answer all questions thoroughly and thoughtfully, showing all work and explanations so that partial grades may be assigned where a complete answer is lacking.

Section 1: Interrupts Define the following terms Interrupt Signal telling the processor to stop its currently running code and execute a different section of code corresponding to the signal Critical Section The section of code that must complete without being interrupted ISR Interrupt Service Routine The code that is run upon an interrupt Assume you are developing a navigational system which has 2 external interrupt sources: a magnetometer which produces readings at 4 millisecond intervals and a GPS sensor which produces readings at 50 millisecond intervals. Further, assume there is an ISR that reads the magnetometer results over SPI and consumes 1 millisecond and another ISR which reads the GPS results over SPI consuming 2 milliseconds and processes the results consuming another 5 milliseconds. Lastly, assume that you must read the result of a sensor before the result is overwritten by the next packet. Explain a strategy for deterministically reading all values from both sensors. You may change the ISR in some way, or discuss other options for creating this operation. You should use nested interrupts giving higher priority to the magnetometer so that it may interrupt the GPS ISR, read a packet, and give control back to the GPS so that you never miss a magnetometer reading. You could optionally move the processing of the GPS results to the main loop.

Section 2: Timers and Counters Explain the difference between a timer and a counter: Timer counts clock transitions, counters count arbitrary signal transition Explain one way you can extend a hardware timer without losing precision: Use the overflow bit as a defacto n+1th bit. Optionally, use the overflow flag to toggle a software counter. Assume you have an 8-bit hardware timer based on a system clock of 1MHz. You have available the following prescalers: 1, 8, 64, 256. Lastly, assume that your timer is set up to toggle an output pin when the counter reaches a value in the output compare register (CTC mode for AVR). Define the prescaler and output compare register in order to achieve a timer that oscillates close to 2,550 hz. 1,000,000/2550 = 392 392 > 255 -- So 392/8 = 49 Therefore, 8 Prescaler, 49- Count register

Section 3: Analog to Digital Converters Explain the successive approximating algorithm that is used in many Analog to Digital Converters: Binary search tree. Compare against half of the voltage and keep a 1 if the(measured) voltage is higher, 0 if the voltage is lower. Proceed through the n-bits until the generated voltage is between two values. (Error upperbounded by 1 LSB precision) How many clock cycles would a 10-bit ADC take to implement the successive approximation algorithm? Binary Search Tree, therefore N clock cycles. The clock cycle length is dependent upon the resolution(precision) of the LSB. Given an ADC which has a 0V ground reference and a 3V top reference, what is the lowest number of bits you need to quantize an ADC with precision of 0.02V or better? 3V-0V/(n^2) = 0.02V 3 / 0.02 = n^2 150 = n^2 Log2(150) = n n ~= 7.22 Because we need a precision of at least 0.02V, we should choose the ceiling of that value to find the number of bits. Therefore we need at least 8 bits.

Section 4: Real Time Operating Systems Describe the difference between thread safe and reentrant code: Thread safe code is safe to be run alongside other code. It locks globals and resources it needs so that if its preempted it still maintains access to those components. Reentrant code is safe to run alongside itself(i.e. the same function being called in multiple places). This is done by locking globals, static variables, and other resources, preventing preemption while holding a lock. (the static variables and preventing preemption especially is how code can be thread-safe but not reentrant). What is a Task Control Block, and what is it useful for? A structure which minimally contains the information about a task, including a pointer to the function the task should run. Useful for RTOS implementation so that queues can be implemented properly. Discuss a strategy for making code thread safe: Mutexes Discuss a strategy for making code reentrant: Local variables, mutexes, avoiding preemption

Section 5: Tasks What is Priority inversion? Give an example of a situation where this could happen: When a task is allowed to run to completion before a task of higher priority because a lower priority task has blocked the higher priority task and been preempted by the priority inverting task. C runs and locks R1. A preempts C and requests R1, gives control to C to release R1. B Preempts C and runs to completion. What is a Ring Buffer? What pieces are needed to build the structure? A circular structure used to store data continuously. You need an array (or any block of memory) and two variables which point to the head and the tail of the data respectively. You should also take care of state variables for when the buffer is empty or full.(prevent overrun or underrun) Choose one of the time-shared scheduling algorithms talked about during lecture (First-Come First- Serve, Shortest Job First, and Round Robin). Given a system which is based off of synchronous tasks, explain an advantage and a disadvantage of using the chosen scheduling algorithm. Round Robin: Advantage : No starvation Disadvantage: High priority tasks may not finish in a guaranteed amount of time