S1V3G340 Development Reference Guide

S1V3G340 Rev.1.00

NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of Economy, Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. SEIKO EPSON CORPORATION 2009, All rights reserved.

Table of Contents 1. Introduction... 1 1.1 Target readership... 1 1.2 Purpose... 1 1.3 Overview... 1 1.4 Manual overview... 2 1.5 Terminology... 2 2. Precautions for Initial Evaluation... 3 3. Development Setup Configuration Examples... 4 3.1 Precautions regarding CASTLE + customer board connection... 5 4. S1V3G340 Control... 7 4.1 Using CASTLE... 7 4.1.1 Flash writing... 7 4.1.2 Function evaluation... 7 4.2 Using Host CPU... 8 4.2.1 Control program development flow... 8 4.2.2 Flash access mode... 8 4.2.3 Flash writing... 9 4.2.4 Function evaluation and control program development... 11 5. Evaluation Development Setup Summary... 12 6. Appendix: Specifications for Flash Memory Writer Sample Program... 13 6.1 Overview... 13 6.2 Obtaining the sample program... 13 6.3 Details of files... 13 6.3.1 main_flashwrite.c... 13 6.3.2 Message file... 13 6.3.3 ROMImage.h... 14 6.4 Specifications for main programs... 14 6.4.1 main_flashwrite.c... 14 6.5 Specifications for S1V3G340 flash memory access control APIs... 18 6.5.1 SPI_Initialize... 18 6.5.2 SPI_SendReceiveByte... 19 6.5.3 SPI_SendMessage... 20 6.5.4 SPI_ReceiveMessage... 21 6.5.5 SPI_SetFlashAccessMode... 22 6.5.6 SPI_EraseFlashData... 23 6.5.7 SPI_WriteFlashData... 24 6.5.8 SPI_VerifyFlashData... 25 6.5.9 GPIO_ControlChipSelect... 26 6.5.10 GPIO_ControlChipReset... 27 Revision History... 28 S1V3G340 Seiko Epson Corporation i

1. Introduction 1. Introduction 1.1 Target readership This document is intended for use by circuit board designers and software designers involved in product development using the S1V3G340. 1.2 Purpose This document is intended primarily to provide examples of development setups for the S1V3G340 and to explain the procedures for writing to SPI-FLASH via the S1V3G340. 1.3 Overview This document contains details of S1V3G340 function evaluation and development setups. A dedicated function evaluation board is not provided for the S1V3G340. The S1V3S344 evaluation board (CASTLE + NIJYO-S) with similar functions should be used for evaluating sound quality or checking the linking of audio data created. This document also describes two examples of methods for writing an ROM image to the SPI-FLASH on customer board, in the form of writing from the host CPU on customer board or by connecting a CASTLE to customer board and writing from that. Note however that when using CASTLE, official support cannot be provided by Seiko Epson due to the use of other manufacturers SPI-FLASH. Table 1.1 shows the correspondence between this document and the S1V3G340 development flow examples. Table 1.1 S1V3G340 development flow examples S1V3G340 Seiko Epson Corporation 1

1. Introduction 1.4 Manual overview This user guide consists of the following sections. Section 2 describes the precautions regarding the S1V3G340 initial evaluation setup. Section 3 describes the overall S1V3G340 development setup. Section 4 describes the control methods for the S1V3G340 development setup. Section 5 summarizes the S1V3G340 evaluation development setup. 1.5 Terminology Table 1.2 explains the terminology used in this document. Table 1.2 Terminology Term Description SPI-FLASH Flash memory using SPI (Serial Peripheral Interface) bus. CASTLE Seiko Epson evaluation board (code: S5U1V3S344E0600) *1 NIJYO-S Seiko Epson evaluation board (code: S5U1V3S344B1600 / S5U1V3S344B0600) *2 Audio data Binary file with extension eov, created using the voice guide generation tool. Compressed audio data. ROM image Binary file with extension bin, created using the voice guide generation tool. Created by linking EOV audio data. ICE Abbreviation for in-circuit emulator. Debugger used for microprocessor board development. Allows software debugging and hardware operation confirmation. Level shift circuit Circuit for converting signal voltage. *1 CASTLE and CASTLE-S are equivalent products. *2 The S5U1V3S344B0600 does not include an explanatory list of CD-ROMs or accompanying items. 2 Seiko Epson Corporation S1V3G340

2. Precautions for Initial Evaluation 2. Precautions for Initial Evaluation A dedicated function evaluation board is not provided for the S1V3G340. The S1V3S344 evaluation board (CASTLE+NIJYO-S, see Figure 2.1) with similar functions can be used for evaluating sound quality or checking the linking of audio data created. For more information about usage procedures, refer to the S1V3S344 Evaluation Board User s Guide. Note that the S1V3S344 mounted on the NIJYO-S board has a flash memory capacity of 512 KB, and so the audio playback demo function described in section 3.1 of the S1V3S344 Evaluation Board User s Guide cannot be used if the ROM image size exceeds 512 KB. In this case, the ROM image playback function described in section 3.2 should be used. Table 2.1 lists the supported functions depending on ROM image size for reference purposes. PC S1V3S344 evaluation kit (CASTLE board + NIJYO-S board) micro SD Card CASTLE C33E07 S1V3S344 NIJYO-S AMP Jack Speaker SW2 Figure 2.1 CASTLE + NIJYO-S Supported function Table 2.1 Supported functions depending on ROM image size Under 512 KB ROM image size 512 KB or more (less than capacity of microsd card included) Audio playback function Support Unsupport ROM image playback function External host connection function (for NIJYO-S only) Flash memory writer function (for CASTLE only) Support Support With following limitation Support Unsupport With following limitation Function description Plays back the audio in accordance with the audio file in the playlist or sequence file. Refer to 3.1 Voice playback in the S1V3S344 Evaluation Board User s Guide. Plays back the entire ROM image file. Refer to 3.2 ROM image playback function in the S1V3S344 Evaluation Board User s Guide. Connects the NIJYO-S to customer host CPU board. Refer to 3.3 External host connection function in the S1V3S344 Evaluation Board User s Guide. Writes the ROM image from the CASTLE to the flash memory via the S1V3S344 on the NIJYO-S or the S1V3G340 on customer board. When writing to the internal flash memory on the S1V3S344 on the NIJYO-S, refer to 3.4 Flash writer function in the S1V3S344 Evaluation Board User s Guide. When writing to the SPI-FLASH memory on customer board, refer to 4.1.1 Flash writing in this document. *3 *3 Writing to SPI-FLASH using CASTLE is not officially supported. Writing is possible from CASTLE, provided the product has similar specifications to the Spansion S25FL016A. S1V3G340 Seiko Epson Corporation 3

3. Development Setup Configuration Examples 3. Development Setup Configuration Examples This document describes the following two examples of configurations for writing ROM images to SPI-FLASH on customer board. 1) Figure 3.1 illustrates a configuration for a development setup with customer board connected to the CASTLE. 2) Figure 3.2 illustrates a configuration for a development setup with customer board connected to a PC. S1V3G340 POWER mini USB microsd CARD HOST CPU SPI FLASH Speaker ICD I/F C33 AMP MCP CASTLE SPI connector Customer board Figure 3.1 Connection diagram for CASTLE + customer board S1V3G340 HOST CPU SPI FLASH Speaker Your ICE AMP ICE connector Customer board Figure 3.2 Connection diagram for PC + customer board The descriptions in this document assume that customer board includes the following components. 1) S1V3G340 2) SPI-FLASH memory 3) Host CPU (microprocessor for system control) 4) Amplifier 5) Speaker 6) External control connector If the S1V3G340 is controlled by the host CPU, an external control connector will be required which allows connection with an ICE supporting your host CPU. Queries about the ICE specifications supporting the host CPU used should be addressed to the manufacturer. If the S1V3G340 is controlled using the CASTLE, however, a connector will be required which allows connection for the signal shown in Table 2.1. Note that methods for controlling the S1V3G340 by connecting the CASTLE to customer board are not officially supported by Seiko Epson due to the use of other manufacturers SPI-FLASH. 4 Seiko Epson Corporation S1V3G340

3. Development Setup Configuration Examples 3.1 Precautions regarding CASTLE + customer board connection Figure 3.3 illustrates the overall system configuration with the CASTLE connected to customer board. The CASTLE should be connected to the S1V3G340 on customer board correctly as shown in Table 3.1. The connection between the S1V3G340 and the host CPU should be Hi-z when controlling the S1V3G340 using the CASTLE. Note that writing directly from the CASTLE to the SPI-FLASH memory is not possible if the power supply voltage is not 3.3 V (Typ.) for customer board, since the CASTLE operates at 3.3 V. Precautions are necessary such as including an appropriate level shift circuit. S1V3G340 POWER mini USB microsd CARD HOST CPU SPI FLASH Speaker ICD I/F C33 AMP Jack MCP CASTLE SPI connector Customer board Figure 3.3 Connection diagram for CASTLE + customer board (same as for Figure 3.1) Mini USB connector Card slot CON1 SW2 DIP-SW1 SW6 Figure 3.4 CASTLE board upper side S1V3G340 Seiko Epson Corporation 5

3. Development Setup Configuration Examples Table 3.1 CASTLE board CON1 (Host I/F connector) pin layout Connector CON1 Pin No. Name I/O Cable color 1 VDD1 P Brown Not used (Open) 2 VDD2 P Red Not used (Open) 3 VDD3 P Orange Not used (Open) 4 CLOCK_IN O Yellow Not used (Open) 5 RESET O Green Not used (Open) Correspondence with S1V3G340 interface pins 6 SCKS O Blue SCKS/SCL (serial interface) 7 SIS O Purple SOS/TXD (serial interface) 8 SOS I Gray SIS/RXD/SDA (serial interface) 9 NSCSS O White NSCSS (serial interface) 10 MSGRDY I Black MSGRDY (serial data output READY) 11 STBYEXIT O Brown Not used (Open) 12 MUTE O Red Not used (Open) 13 VSS P Orange VSS 14 VSS P Yellow VSS 15 VSS P Green Not used (Open) 16 VSS P Blue Not used (Open) 6 Seiko Epson Corporation S1V3G340

4. S1V3G340 Control 4. S1V3G340 Control This section describes the methods for controlling the S1V3G340 on customer board. 4.1 Using CASTLE and 4.2 Using Host CPU correspond respectively to Figures 3.1 and 3.2 in 3. Development Setup Configuration Examples. 4.1 Using CASTLE 4.1.1 Flash writing The operating procedures are described below for writing a ROM image to the SPI-FLASH memory connected externally via S1V3G340 using the CASTLE. *4 Note that when writing to the SPI-FLASH memory using the CASTLE, all of the data within the SPI-FLASH memory will be deleted. (1) Copy the ROM image file created on the PC using the Epson Speech IC Speech Guide Creation Tool to the micro SD card. (2) Insert the micro SD card onto which the ROM image file has been copied into the card slot on the CASTLE board. (3) Connect the CASTLE board to customer board. (Refer to 3.1 Precautions regarding CASTLE + customer board connection. ) (4) Set the CASTLE DIP-SW1 as shown in Table 4.1 below. Table 4.1 DIP-SW1 settings (CASTLE) SW1-1 SW1-2 SW1-3 SW1-4 SW1-5 SW1-6 Don t care ON OFF Don t care Don t care ON (5) Insert the micro SD card containing the ROM image into the CASTLE board. (6) Connect the CASTLE to the power supply battery pack using a USB cable. (7) Press the reset switch (SW6) on the CASTLE board. (8) Press the Start/Stop switch (SW2) on the CASTLE board to start writing to the SPI-FLASH memory externally connected. (9) The LEDs all illuminate and flash writing ends. * Writing will take several minutes to complete. (10) Press the reset switch (SW6) on the CASTLE board. *4 Writing to SPI-FLASH using CASTLE is not officially supported. Writing is possible from CASTLE, provided the product has similar specifications to the Spansion S25FL016A. 4.1.2 Function evaluation Function evaluation using the CASTLE allows execution of the details described in 3.1 Voice playback of the S1V3S344 Evaluation Board User s Guide. S1V3G340 Seiko Epson Corporation 7

4. S1V3G340 Control 4.2 Using Host CPU 4.2.1 Control program development flow The procedures for S1V3G340 control program development are described below. 1) Create a ROM image using the Epson Speech IC Speech Guide Creation Tool. 2) Create a program for writing data to flash memory. (Refer to Figure 4.2, Example SPI-FLASH writing flowchart. ) 3) Run the flash writing program using the host CPU to write the ROM image to the SPI-FLASH memory. 4) Create the S1V3G340 control program. 4.2.2 Flash access mode The S1V3G340 is capable of sequence playback for continuous playback of specified audio data by writing a ROM image created using the Epson Speech IC Speech Guide Creation Tool to the SPI-FLASH memory connected externally. For more information about creating a ROM image, refer to the Epson Speech IC Speech Guide Creation Tool User Guide. For more information about sequence playback, refer to 4.9 Sequenced Playback Messages of the S1V3034x Series Message Protocol Specification. The S1V3G340 must be set to FLASH access mode when writing a ROM image to the SPI-FLASH memory via the S1V3G340. For details of the setting procedure, refer to 3. FLASH Access Mode Setup of the FLASH Access Specifications. When in FLASH access mode, signals from the host CPU will bypass the S1V3G340 and be sent directly to the SPI-FLASH. This is therefore the same as having the host CPU connected directly to the SPI-FLASH. For more information on the FLASH access mode setting procedure, refer to Figure 4.2, Example SPI-FLASH writing flowchart. S1V3G340 in flash access mode HOST CPU S1V3G340 ) SPI FLASH HOST CPU SPI FLASH Figure 4.1 Host CPU and SPI-FLASH connection schematic 8 Seiko Epson Corporation S1V3G340

4. S1V3G340 Control 4.2.3 Flash writing The S1V3G340 must be set to FLASH access mode when writing a ROM image to externally connected SPI-FLASH memory via the S1V3G340 using the host CPU. After setting the S1V3G340 to FLASH access mode, write the ROM image in accordance with the specifications for the SPI-FLASH used. Figure 4.2 illustrates a typical flowchart for writing a ROM image to SPI-FLASH via the S1V3G340. The FLASH writing program must be created in accordance with this flowchart. In this example, data is read one byte at a time after writing N bytes of data to verify that the data written is correct. S1V3G340 Seiko Epson Corporation 9

4. S1V3G340 Control Start Initialize host CPU Acquire N bytes of write data S1V3G340 HW Reset Write sequence NSCSS -> L Write N bytes to SPI-FLASH Refer to specifications manual for the SPI-FLASH that you use. Wait time of 120 ms Send/receive ISC_RESET_REQ/RESP Send ISC_SPISW_IND Read sequence NSCSS -> H Wait time of 5 μs Read 1 byte from SPI-FLASH Refer to specifications manual for the SPI-FLASH that you use. Acquire ROM image file size Erasure sequence Is the data correct? No Erase all SPI-FLASH data Refer to specifications manual for the SPI-FLASH that you use. No Yes N bytes received? Yes Increment write data address by N bytes Verification error End due to error No Volume of data written ROM image file capacity Yes End Figure 4.2 Example SPI-FLASH writing flowchart 10 Seiko Epson Corporation S1V3G340

4. S1V3G340 Control 4.2.4 Function evaluation and control program development Sample programs should be downloaded from the Evaluation Kit Download Site on the Seiko Epson Semiconductor Device website for use in S1V3G340 function evaluation and control program development. For more information about sample program specifications, refer to 7. Sample Program Specifications of the S1V3034x Series Message Protocol Specification. The sample program allows evaluation of the streaming playback function for playback while receiving audio data from the host CPU in real time, the sequence playback function for reading and playing back specified audio data from the SPI-FLASH memory connected externally, and standby mode for reducing the power consumption. Note that this sample program does not include a FLASH writing function. S1V3G340 Seiko Epson Corporation 11

5. Evaluation Development Setup Summary 5. Evaluation Development Setup Summary This section summarizes the S1V3G340 evaluation development setup described in previous sections. Table 5.1 S1V3G340 evaluation development setup summary Phase Initial evaluation Board audio quality evaluation (Can be omitted) Program development Devices used CASTLE + NIJYO-S (Figure 2.1) Speaker CASTLE + customer board (Figure 3.1) Speaker Customer board (Figure 3.2) Speaker PC ICE ROM image location Micro SD card Sound quality evaluation Operations possible SPI- FLASH writing Host CPU Program debugging Support Unspport Unspport SPI-FLASH Support Support Unspport SPI-FLASH Support Support Support Related documents S1V3S344 Evaluation Board User s Guide 3.1 Voice playback 3.2 ROM image playback function *5 S1V3S344 Evaluation Board User s Guide 3.1 Voice playback S1V3G340 Hardware Specification S1V3G340 Development Reference Guide 3. Development Configuration Setup Examples 4.1 Using CASTLE S1V3G340 Hardware Specification S1V3G340 Development Reference Guide 3. Development Configuration Setup Examples 4.2 Using Host CPU FLASH Access Specifications S1V3034x Series Message Protocol Specification *5 The audio playback demo function described in section 3.1 of the S1V3S344 Evaluation Board User s Guide can be used for initial evaluation, but it cannot be used with ROM images exceeding 512 KB in size, since ROM images are stored in the flash memory inside the S1V3S344 mounted on the NIJYO-S. 12 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program 6. Appendix: Specifications for Flash Memory Writer Sample Program 6.1 Overview This section provides specifications for the flash memory writer sample program provided to the S1V3G340 user. This program is a sample program designed to control access to flash memory in the S1V3G340 operating on your host system. Also given below are the specifications for the APIs contained in the sample program. * This sample program was created for the host system used for S1V3G340 control evaluations performed by Seiko Epson by connecting the Spansion S25FL016A as the external SPI-FLASH. We do not guarantee the compatibility of the sample program when used in your system. 6.2 Obtaining the sample program You must download the sample program from the Epson Speech & Audio Evaluation Kit Download Site. Please refer to the document enclosed in the S1V3G340 evaluation kit for the Epson Speech & Audio Evaluation Kit Download Site URL. 6.3 Details of files The sample program is stored in the following directory. \flash Source files for the flash memory writer sample program are stored. * When the sample program is incorporated into your system, some source code must be modified to suit the system used. 6.3.1 main_flashwrite.c The main_flashwrite.c file describes a series of control programs for performing flash access processing based on control from the host processor. 6.3.2 Message file The message file defines the REQ message array table. The message file defines data similar to the data shown in Figure 6.1. It describes the REQ message data array, including the message header, 0x00, 0xAA. unsigned char auciscresetreq[] = { 0x00, 0xAA, 0x01, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, }; Figure 6.1 Example of message file S1V3G340 Seiko Epson Corporation 13

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.3.3 ROMImage.h In the ROMImage.h file, specify the start address for the binary data of the ROM image file (ROMImage_YYMMDD_HHMMSS.bin) and the size of the ROM image. Table 6.1 List of source files Filename Directory Description main_flashwrite.c flash Main program for writing data to flash memory Isc_msgs.c flash REQ message array table definition file for standard-version sample program Isc_msg.h flash Header file of REQ message array table definition file for standard-version sample program ROMImage.h flash Designation of ROM image spi_api.c flash SPI control API function definition *1 spi_api.h flash SPI control API function declaration reg.h flash SPI register map definition *2 *1 spi_api.c is a control program prepared for the SPI in the host system used by Seiko Epson for S1V3G340 control evaluations. When incorporated into your system, it must be modified to suit the system used. *2 reg.h describes the map of SPI registers in the host system used by Seiko Epson for S1V3G340 control evaluations. When incorporated into your system, it must be modified to suit the SPI specifications of the host system used. 6.4 Specifications for main programs The sample program provides main programs for writing data to flash memory. Each main program provides control according to the procedure described below. For more information about S1V3G340 SPI command transmission, refer to the S1V3034x Message Protocol Specification. For more information about the FLASH access SPI command specifications, refer to the specifications and manual for the SPI-FLASH used. (This sample program describes an example using the Spansion S25FL016A specifications.) * This sample program does not use interrupt processing. If your host system requires interrupt processing, you must make the necessary changes based on the interruption specifications of the host system used. 6.4.1 main_flashwrite.c This is a main program used to write data to flash memory. It initializes the system and writes ROM image file to flash memory. The flowchart is shown on the next page. 14 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program Start Write sequence Acquire 1,024 bytes of ROM image file data from uladdress Initialize host CPU uldatasize = 1024 S1V3G340 HW Reset NSCSS -> L Send WE command (0x06) Initialize SPI I/F NSCSS -> H NSCSS -> L Wait time of 120 ms Send/receive ISC_RESET_REQ/RESP NSCSS -> L Send Write command (0x02) Send write data (256 bytes) NSCSS -> H Send ISC_SPISW_IND NSCSS -> L NSCSS -> H No RDSR[bit0] = 0? Wait time of 5 μs Acquire ROM image file size (ulromsize) uladdress = 0 NSCSS -> H Yes uldatasize -= 256 Erasure sequence NSCSS -> L No uldatasize = 0? Send WE command (0x06) Read sequence Yes NSCSS -> L NSCSS -> H Send Read command (0x03) NSCSS -> L Receive 1 byte from serial I/F Send Erase command (0x07) NSCSS -> H Is the data correct? Yes No NSCSS -> L No 1,024 bytes received? Verification error No RDSR[bit0] = 0? NSCSS -> H Yes End due to error Yes NSCSS -> H ulromsize = ulromsize 1024 uladdress += 1024 No ulromsize = 0? Yes End Figure 6.2 Main program flowchart S1V3G340 Seiko Epson Corporation 15

6. Appendix: Specifications for Flash Memory Writer Sample Program (1) Initializes the system. (2) Executes a hardware reset for the S1V3G340. (3) Initializes the SPI I/F module. (4) Sets the S1V3G340 s NSCSS (Chip Select) to L. (5) Guarantees 120-ms wait time for the S1V3G340. (6) Resets the S1V3G340. (Transmission/reception of ISC_RESET_REQ/RESP) (7) Sets the S1V3G340 to Flash Access mode. (Transmission of ISC_SPISW_IND) (8) Sets the S1V3G340 s NSCSS (Chip Select) to H. (9) Guarantees 5-μs wait time for the S1V3G340. (10) Acquires the ROM image file size. -------------------------------- Erasure sequence start --------------------------------------- (11) Sets the external SPI-FLASH chip select signal to L. (12) Enables WE for external SPI-FLASH. (Transmission of 0x06 by SPI) (13) Sets the external SPI-FLASH chip select signal to H. (14) Sets the external SPI-FLASH chip select signal to L. (15) Deletes the external SPI-FLASH contents. (Transmission of 0xC7 by SPI) (16) Sets the external SPI-FLASH chip select signal to H. (17) Sets the external SPI-FLASH chip select signal to L. (18) Reads the status register (RDSR) from the external SPI-FLASH. (Transmission of 0x05 by SPI) (19) Receives repeatedly until the status register (RDSR) bit0 reaches 0. (To complete the deletion sequence for the external SPI-FLASH) (20) Sets the external SPI-FLASH chip select signal to H. -------------------------------- Erasure sequence end -------------------------------------- -------------------------------- Write sequence start ----------------------------------------- (21) Acquires data for writing to FLASH. (Acquires 1,024 bytes of data from the ROM image file.) (22) Sets the external SPI-FLASH chip select signal to L. (23) Enables WE for external SPI-FLASH. (Transmission of 0x06 by SPI) (24) Sets the external SPI-FLASH chip select signal to H. (25) Sets the external SPI-FLASH chip select signal to L. (26) Starts writing to external SPI-FLASH. (Sends 0x02 using SPI, writing start address is 24 bits, 256 byte continuous writing) (27) Sets the external SPI-FLASH chip select signal to H. (28) Sets the external SPI-FLASH chip select signal to L. (29) Reads the status register (RDSR) from the external SPI-FLASH. (Transmission of 0x05 by SPI) 16 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program (30) Receives repeatedly until the RDSR bit0 reaches 0. (To complete the writing sequence for the external SPI-FLASH) (31) Sets the external SPI-FLASH chip select signal to H. (32) Repeat steps (22) to (31) until 1,024 bytes are written. -------------------------------- Write sequence end ----------------------------------------- -------------------------------- Read sequence start ----------------------------------------- (33) Sets the external SPI-FLASH chip select signal to L. (34) Starts reading from external SPI-FLASH. (Sends 0x03 using SPI, read address is 24 bits.) (35) Reads only 1,024 bytes of data while comparing against data written in (21) to (32). Returns an error if comparison discrepancies arise. (36) Sets the external SPI-FLASH chip select signal to H. -------------------------------- Read sequence end ----------------------------------------- (37) Repeat steps (21) to (36) until entire ROM image file has been written. < ROM image file writing complete > S1V3G340 Seiko Epson Corporation 17

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5 Specifications for S1V3G340 flash memory access control APIs Given below are the specifications for the APIs for accessing the S1V3G340 s flash memory. * Shown below is the control program prepared for the SPI in the host system used by Seiko Epson for S1V3G340 control evaluations. When incorporated into your system, the contents of the APIs must be modified to suit the system used. 6.5.1 SPI_Initialize [Syntax] void SPI_Initialize (void) [Function] Initializes the SPI. [Input argument] [Output argument] [Return value] [Function description] This function initializes the registers of the SPI. This API function complies with the specifications of the SPI of the host processor used in Seiko Epson s evaluation system and makes the following settings. (1) Disables the SPI module. (2) Sets the input/output pins. (3) Sets the SPI clock frequency. *1 (4) Sets the SPI clock mode (polarity and phase). (5) Sets the SPI to Master mode. (6) Sets the wait cycle between data transfers. (7) Sets the bit mask for received data. (8) Disables interrupts for the SPI module. (9) Enables the SPI module. (10) Disables the SD Card SPI access. (Because SPI I/F is shared) *1 The SPI s maximum clock frequency for flash memory access is 1.024 MHz. 18 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.2 SPI_SendReceiveByte [Syntax] unsigned char SPI_SendReceiveByte ( unsigned char ucsenddata) [Function] Sends and receives 1-byte data. [Input argument] ucsenddata Sets 1-byte transmission data. [Output argument] [Return value] Returns 1-byte received data. [Function description] This function simultaneously sends and receives one-byte data to and from the S1V3G340 via the SPI. S1V3G340 Seiko Epson Corporation 19

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.3 SPI_SendMessage [Syntax] int SPI_SendMessage ( unsigned char *pucsendmessage, unsigned short *pusreceivedmessageid) [Function] Sends messages to the S1V3G340. [Input argument] pucsendmessage Specifies the address of the memory area in which the transmitted message is stored. pusreceivedmessageid Specifies the pointer to the variable that stores the message ID of the message received during data transmission. [Output argument] [Return value] Returns 0 when the process is completed successfully; otherwise returns -1. [Function description] This function sends REQ messages to the S1V3G340. It refers to the value in the length field of the target REQ message when sending data. If a message from the S1V3G340 is received during transmission of the REQ message, the ID of that message is stored in pusreceivedmessageid. * This is a message transmission function for the standard-version sample program. 20 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.4 SPI_ReceiveMessage [Syntax] int SPI_ReceiveMessage ( unsigned short *pusreceivedmessageid, ) [Function] Receives messages from the S1V3G340. [Input argument] [Output argument] pusreceivedmessageid Specifies the pointer to the variable that stores the message ID of the received message. [Return value] Returns 0 when the process is completed successfully; otherwise returns -1. [Function description] This function receives the RESP or IND message issued from the S1V3G340. It continues receiving data from the S1V3G340 until it detects the message header (0x00, 0xAA). Thereafter, this function obtains the values in the length field and id field in the received message and continues receiving data based on the obtained length field value. The obtained id field value is stored in the output argument pucreceivedmessageid. The function also performs error processing (e.g., ID checks) for the received message. S1V3G340 Seiko Epson Corporation 21

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.5 SPI_SetFlashAccessMode [Syntax] void SPI_SetFlashAccessMode (void) [Function] Sets the S1V3G340 to Flash Access mode. [Input argument] [Output argument] [Return value] [Function description] Sets the S1V3G340 to Flash Access mode. * Described below is the detailed process flow. * For more details, refer to the FLASH Access Specifications. (1) Sets NSCSS (Chip Select) to L. (2) Sends 0x00 0xaa 0x04 0x00 0x00 0xFF (6 bytes) in that sequence to the serial communication interface. (3) Sets NSCSS (Chip Select) to H. (4) Guarantees 5-μs wait time to the S1V3G340. (5) The S1V3G340 enters Flash Access mode. 22 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.6 SPI_EraseFlashData [Syntax] void SPI_EraseFlashData (void) [Function] Executes the flash memory erasure sequence for external SPI-FLASH. [Input argument] [Output argument] [Return value] [Function description] Executes the flash memory erasure sequence * for external SPI-FLASH. Described below is the detailed process flow. * The S1V3G340 must be in Flash Access mode to execute the flash memory erasure sequence. Before calling this function, be sure to invoke the SPI_SetFlashAccessMode function to set the S1V3G340 to Flash Access mode. (For more details, refer to the FLASH Access Specifications.) (1) Sets the chip select signal to L. (2) Sends 0x06 to the serial communication interface. (Write enable) (3) Sets the chip select signal to H. (4) Sets the chip select signal to L. (5) Sends 0xC7 to the serial communication interface. (6) Sets the chip select signal to H. (7) Sets the chip select signal to L. (8) Sends 0x05 to the serial communication interface. (9) Receives the status register (RDSR). Receives repeatedly until the RDSR bit0 reaches 0. (10) Sets the chip select signal to H. (11) Completes the chip erasure process. S1V3G340 Seiko Epson Corporation 23

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.7 SPI_WriteFlashData [Syntax] void SPI_WriteFlashData (unsigned long uladdress, unsigned char *pucdata unsigned long uldatasize) [Function] Executes the flash memory erasure sequence for external SPI-FLASH. [Input argument] uladdress Flash write start address (24-bit specification) pucdata Pointer to the data to be written to flash memory uldatasize Flash write data size [Output argument] [Return value] [Function description] Executes the flash memory erasure sequence *1 for external SPI-FLASH. This function issues a write command and writes uldatasize bytes of data to the flash memory. Described below is the detailed process flow. (1) Sets NSCSS (Chip Select) to L. (2) Sends 0x06 to the serial communication interface. (Write enable) (3) Sets NSCSS (Chip Select) to H. (4) Sets NSCSS (Chip Select) to L. (5) Sends 0x02 to the serial communication interface. (6) Sends the 24-bit address and write data (max 256 bytes per block) to the serial communication interface. (7) Sets NSCSS (Chip Select) to H. (8) Sets NSCSS (Chip Select) to L. (9) Sends 0x05 to the serial communication interface. (10) Receives the status register (RDSR). Receives repeatedly until the RDSR bit0 reaches 0. (11) Sets NSCSS (Chip Select) to H. (12) Ends writing for 1 block (flash memory write sequence). (13) Repeat steps (1) to (12) until uldatasize bytes are written. (14) End *1 The S1V3G340 must be in Flash Access mode to execute the flash memory write sequence. Before calling this function, be sure to invoke the SPI_SetFlashAccessMode function to set the S1V3G340 to Flash Access mode. (For more information, refer to the FLASH Access Specifications.) 24 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.8 SPI_VerifyFlashData [Syntax] int SPI_VerifyFlashData (unsigned long uladdress, unsigned char auccompdata[], unsigned long ulcompdatasize) [Function] Executes the flash memory read sequence in the S1V3G340 and checks whether the read data is correct. [Input argument] uladdress Flash read start address (24-bit specification) auccompdata Comparison source data array ulcompdatasize Flash read data size [Output argument] [Return value] Returns 0 when the process is completed successfully or returns -5 when a verification error occurs. [Function description] This function executes the flash memory read sequence *1 for external SPI-FLASH and checks whether the read data is correct. (1) Sets the chip select signal to L. (2) Sends 0x03 to the serial communication interface. (3) Receives 1-byte data from the serial communication interface and checks whether it corresponds to the auccompdata array data. Returns an error and ends the process if a comparison error occurs. *2 (4) Repeats step (3) for the number of times corresponding to ulcompdatasize. (5) Sets the chip select signal to H. (6) End *1 The S1V3G340 must be in Flash Access mode to execute the flash memory read sequence. Before calling this function, be sure to invoke the SPI_SetFlashAccessMode function to set the S1V3G340 to Flash Access mode. (For more information, refer to the FLASH Access Specifications.) *2 If a verification error occurs, enable the H/W Reset of the S1V3G340 and repeat the process from the beginning. S1V3G340 Seiko Epson Corporation 25

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.9 GPIO_ControlChipSelect [Syntax] void GPIO_ControlChipSelect ( int ivalue) [Function] Controls the NSCSS (Chip Select signal) of the S1V3G340. [Input argument] ivalue Specifies 0: L or 1: H. [Output argument] [Return value] [Function description] Controls the NSCSS (Chip Select signal) of the S1V3G340. To initiate communications with the S1V3G340 by means of the serial communication interface, you must set NSCSS to L. 26 Seiko Epson Corporation S1V3G340

6. Appendix: Specifications for Flash Memory Writer Sample Program 6.5.10 GPIO_ControlChipReset [Syntax] void GPIO_ControlChipReset (void) [Function] Executes hardware reset for the S1V3G340. [Input argument] [Output argument] [Return value] [Function description] This function executes hardware reset for the S1V3G340. Specifically, it controls the H/WReset signal (NRESET) of the S1V3G340 and applies a hardware reset. You must invoke this function to initialize the S1V3G340 when initializing the program or when rebooting the program after a verification error. S1V3G340 Seiko Epson Corporation 27

Revision History Revision History Attachment-1 Rev. No. Date Page Type Revision details (including previous details) and reason Rev. 0.10 03/19/2009 All New New issue Rev. 0.20 03/24/2009 2 3 11 Addition Addition Addition Added 1.5 Terminology. Added 2. Precautions for Initial Evaluation. Added 5. Evaluation Development Setup Summary. Rev. 1.00 05/11/2009 15 Addition Added 6. Specifications for Flash Memory Writer Sample Program. 28 Seiko Epson Corporation S1V3G340

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